Datasheet

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Revision 1.92 (06-27-11) 68 SMSC LAN91C111 REV C
DATASHEET
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal
errors occurs:
 SQET - SQE Error
 LOST CARR - Lost Carrier
 LATCOL - Late Collision
 16COL - 16 collisions
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is
always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet
number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT
bit set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be
read from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY
bit in the FIFO PORTS register.
Receive Interrupt is cleared when RX FIFO is empty.