Datasheet

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SMSC LAN91C111 REV C 57 Revision 1.92 (06-27-11)
DATASHEET
8.13 Bank 1 - Individual Address Registers
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or
EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not
modify the EEPROM Individual Address contents. Bit 0 of Individual Address 0 register corresponds
to the first bit of the address on the cable.
OFFSET NAME TYPE SYMBOL
4 THROUGH 9
INDIVIDUAL ADDRESS
REGISTERS READ/WRITE IAR
LOW
BYTE
ADDRESS 0
00000000
HIGH
BYTE
ADDRESS 1
00000000
LOW
BYTE
ADDRESS 2
00000000
HIGH
BYTE
ADDRESS 3
00000000
LOW
BYTE
ADDRESS 4
00000000
HIGH
BYTE
ADDRESS 5
00000000