Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

SMSC LAN9118 87 Revision 1.5 (07-11-08)

DATASHEET

5.3.18 FREE_RUN—Free-Run 25MHz Counter

This register reflects the value of the free-running 25MHz counter.

5.3.19 RX_DROP– Receiver Dropped Frames Counter

This register indicates the number of receive frames that have been dropped.

Offset: 9Ch Size: 32 bits

BITS DESCRIPTION TYPE DEFAULT

31:0 Free Running SCLK Counter (FR_CNT):

Note: This field reflects the value of a free-running 32-bit counter. At reset

the counter starts at zero and is incremented for every 25MHz

cycle. When the maximum count has been reached the counter will

rollover. When read in 16-bit mode the count value is latched on

the first read. The FREE_RUN counter can take up to 160nS to

clear after a reset event.

Note: This counter will run regardless of the power management states

D0, D1 or D2.

RO -

Offset: A0h Size: 32 bits

BITS DESCRIPTION TYPE DEFAULT

31-0 RX Dropped Frame Counter (RX_DFC). This counter is incremented every

time a receive frame is dropped. RX_DFC is cleared on any read of this

An interrupt can be issued when this counter passes through its halfway

point (7FFFFFFFh to 80000000h).

RC 00000000h