Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118 85 Revision 1.5 (07-11-08)
DATASHEET
5.3.15 GPT_CFG-General Purpose Timer Configuration Register
This register configures the General Purpose timer. The GP Timer can be configured to generate host
interrupts at intervals defined in this register.
4:3 GPO Data 3-4 (GPODn). The value written is reflected on GPOn.
GPO3 – bit 3
GPO4 – bit 4
R/W 00
2:0 GPIO Data 0-2 (GPIODn).
When enabled as an output, the value written is
reflected on GPIOn. When read, GPIOn reflects the current state of the
corresponding GPIO pin.
GPIO0 – bit 0
GPIO1 – bit 1
GPIO2 – bit 2
R/W 000
Table 5.4 EEPROM Enable Bit Definitions
[22] [21] [20] EEDIO FUNCTION EECLK FUNCTION
0 0 0 EEDIO EECLK
0 0 1 GPO3 GPO4
0 1 0 Reserved
0 1 1 GPO3 RX_DV
1 0 0 Reserved
1 0 1 TX_EN GPO4
1 1 0 TX_EN RX_DV
11 1 TX_CLK RX_CLK
Offset: 8Ch Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31-30 Reserved RO -
29 GP Timer Enable (TIMER_EN). When a one is written to this bit the GP
Timer is put into the run state. When cleared, the GP Timer is halted. On
the 1 to 0 transition of this bit the GPT_LOAD field will be preset to FFFFh.
R/W 0
28-16 Reserved RO -
15-0 General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded
into the GP-Timer.
R/W FFFFh
Bits Description Type Default