Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.5 (07-11-08) 80 SMSC LAN9118
DATASHEET
5.3.10 RX_DP_CTRL—Receive Datapath Control Register
This register is used to discard unwanted receive frames.
5.3.11 RX_FIFO_INF—Receive FIFO Information Register
This register contains the used space in the receive FIFOs of the LAN9118 Ethernet Controller.
Offset: 78h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31 RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes
the RX data FIFO to fast-forward to the start of the next frame. This bit will
remain high until the RX data FIFO fast-forward operation has completed.
No reads should be issued to the RX data FIFO while this bit is high.
Note: Please refer to section “Receive Data FIFO Fast Forward” on
page 54 for detailed information regarding the use of RX_FFWD.
R/W 0h
30-0 Reserved RO -
Offset: 7Ch Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31-24 Reserved RO -
23-16 RX Status FIFO Used Space (RXSUSED). Indicates the amount of space
in DWORDs, used in the RX Status FIFO.
RO 00h
15-0 RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in
bytes, used in the RX data FIFO. For each receive frame, this field is
incremented by the length of the receive data rounded up to the nearest
DWORD (if the payload does not end on a DWORD boundary).
RO 0000h