Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.5 (07-11-08) 78 SMSC LAN9118
DATASHEET
configuration (HW_CFG) register. The TX_FIF_SZ field selects the total allocation for the TX data path,
including the TX Status FIFO size. The TX Status FIFO size is fixed at 512 Bytes (128 TX Status
DWORDs). The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder
being the TX data FIFO Size. Note that TX data FIFO space includes both commands and payload
data.
RX FIFO Size is the remainder of the unallocated FIFO space (16384 bytes – TX FIFO Size). The RX
Status FIFO size is always equal to 1/16 of the RX FIFO Size. The RX Status FIFO length is subtracted
from the total RX FIFO size with the remainder being the RX data FIFO Size.
For example, if TX_FIF_SZ = 6 then:
Total TX FIFO Size = 6144 Bytes (6KB)
TX Status FIFO Size = 512 Bytes (Fixed)
TX Data FIFO Size = 6144 – 512 = 5632 Bytes
RX FIFO Size = 16384 – 6144 = 10240 Bytes (10KB)
RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs)
RX Data FIFO Size = 10240 – 640 = 9600 Bytes
Table 5.3 shows every valid setting for the TX_FIF_SZ field. Note that settings not shown in this table
are reserved and should not be used.
Note: The RX data FIFO is considered full 4 DWORDs before the length that is specified in the
HW_CFG register.
In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K
bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by
the host.
Table 5.3 Valid TX/RX FIFO Allocations
TX_FIF_SZ
TX DATA FIFO
SIZE (BYTES)
TX STATUS FIFO
SIZE (BYTES)
RX DATA FIFO
SIZE (BYTES)
RX STATUS FIFO
SIZE (BYTES)
2 1536 512 13440 896
3 2560 512 12480 832
4 3584 512 11520 768
5 4608 512 10560 704
6 5632 512 9600 640
7 6656 512 8640 576
8 7680 512 7680 512
9 8704 512 6720 448
10 9728 512 5760 384
11 10752 512 4800 320
12 11776 512 3840 256
13 12800 512 2880 192
14 13824 512 1920 128