Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118 71 Revision 1.5 (07-11-08)
DATASHEET
5.3.3 INT_STS—Interrupt Status Register
This register contains the current status of the generated interrupts. Writing a 1 to the corresponding
bits acknowledges and clears the interrupt.
Offset: 58h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31 Software Interrupt (SW_INT). This interrupt is generated when the
SW_INT_EN bit is set high. Writing a one clears this interrupt.
R/WC 0
30-26 Reserved RO -
25 TX Stopped (TXSTOP_INT). This interrupt is issued when STOP_TX bit
in TX_CFG is set, and the transmitter is halted.
R/WC 0
24 RX Stopped (RXSTOP_INT). This interrupt is issued when the receiver is
halted.
R/WC 0
23 RX Dropped Frame Counter Halfway (RXDFH_INT). This interrupt is
issued when the RX Dropped Frames Counter counts past its halfway
point (7FFFFFFFh to 80000000h).
R/WC 0
22 Reserved RO 0
21 TX IOC Interrupt (TX_IOC). When a buffer with the IOC flag set has
finished being loaded into the TX FIFO, this interrupt is generated.
R/WC 0
20 RX DMA Interrupt (RXD_INT). This interrupt is issued when the amount
of data programmed in the RX DMA Count (RX_DMA_CNT) field of the
RX_CFG register has been transferred out of the RX FIFO.
R/WC 0
19 GP Timer (GPT_INT).
This interrupt is issued when the General Purpose
timer wraps past zero to FFFFh.
R/WC 0
18 PHY (PHY_INT).
Indicates a PHY Interrupt event. RO 0
17 Power Management Event Interrupt (PME_INT). This interrupt is issued
when a Power Management Event is detected as configured in the
PMT_CTRL register. This interrupt functions independent of the PME
signal, and will still function if the PME signal is disabled. Writing a '1'
clears this bit regardless of the state of the PME hardware signal.
Notes:
 Detection of a Power Management Event, and assertion of the PME
signal will not wakeup the LAN9118. The LAN9118 will only wake up
when it detects a host write cycle of any data to the BYTE_TEST
register.
 The Interrupt Deassertion interval does not apply to the PME interrupt.
R/WC 0
16
TX Status FIFO Overflow (TXSO). Generated when the TX Status
FIFO overflows.
R/WC 0
15
Receive Watchdog Time-out (RWT). Interrupt is generated when a
packet larger than 2048 bytes has been received.
R/WC 0
14
Receiver Error (RXE). Indicates that the receiver has encountered an
error. Please refer to Section 3.13.5, "Receiver Errors," on page 56 for a
description of the conditions that will cause an RXE.
R/WC 0
13
Transmitter Error (TXE). When generated, indicates that the
transmitter has encountered an error. Please refer to Section 3.12.7,
"Transmitter Errors," on page 52, for a description of the conditions that
will cause a TXE.
R/WC 0