Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118 69 Revision 1.5 (07-11-08)
DATASHEET
5.3.1 ID_REV—Chip ID and Revision
This register contains the ID and Revision fields for this design.
9Ch FREE_RUN Free Run Counter -
A0h RX_DROP RX Dropped Frames Counter 00000000h
A4h MAC_CSR_CMD MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
00000000h
A8h MAC_CSR_DATA MAC CSR Synchronizer Data 00000000h
ACh AFC_CFG Automatic Flow Control Configuration 00000000h
B0h E2P_CMD EEPROM command (The EEPROM is
indexed through this register)
00000000h
B4h E2P_DATA EEPROM Data 00000000h
B8h - FCh RESERVED Reserved for future use -
Offset: 50h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31-16 Chip ID. This read-only field identifies this design RO 0118h
15-0 Chip Revision. This is the current revision of the chip. RO 0001h
Table 5.1 LAN9118 Direct Address Register Map (continued)
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET SYMBOL REGISTER NAME DEFAULT