Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.5 (07-11-08) 68 SMSC LAN9118
DATASHEET
5.2.2 TX FIFO Ports
The TX data Path consists of two FIFOs, the TX status and data. The TX Status FIFO can be read
from two locations. The TX Status FIFO Port will perform a destructive read, thus “Popping” the data
from the TX Status FIFO. There is also the TX Status FIFO PEEK location. This location allows a non-
destructive read of the top (oldest) location of the FIFO.
The TX data FIFO is Write Only. It is aliased in 8 DWORD locations (16 WORD locations in 16-bit
mode) from the 20h offset to 3Ch offset. The host may write to any of the 8(16) locations since they
all access the same TX data FIFO location and perform the same function.
5.3 System Control and Status Registers
Table 5.1, "LAN9118 Direct Address Register Map", lists the registers that are directly addressable by
the host bus.
Table 5.1 LAN9118 Direct Address Register Map
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET SYMBOL REGISTER NAME DEFAULT
50h ID_REV Chip ID and Revision. See “ID_REV—
Chip ID and
Revision” on
page 69.
54h IRQ_CFG Main Interrupt Configuration 00000000h
58h INT_STS Interrupt Status 00000000h
5Ch INT_EN Interrupt Enable Register 00000000h
60h RESERVED Reserved for future use -
64h BYTE_TEST Read-only byte order testing register 87654321h
68h FIFO_INT FIFO Level Interrupts 48000000h
6Ch RX_CFG Receive Configuration 00000000h
70h TX_CFG Transmit Configuration 00000000h
74h HW_CFG Hardware Configuration 00050000h
78h RX_DP_CTL RX Datapath Control 00000000h
7Ch RX_FIFO_INF Receive FIFO Information 00000000h
80h TX_FIFO_INF Transmit FIFO Information 00001200h
84h PMT_CTRL Power Management Control 00000000h
88h GPIO_CFG General Purpose IO Configuration 00000000h
8Ch GPT_CFG General Purpose Timer Configuration 0000FFFFh
90h GPT_CNT General Purpose Timer Count 0000FFFFh
94h RESERVED Reserved for future use -
98h WORD_SWAP WORD SWAP Register 00000000h