Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

SMSC LAN9118 37 Revision 1.5 (07-11-08)

DATASHEET

WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the

contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit

is set if the EEPROM does not respond within 30ms.

Figure 3.10 EEPROM WRAL Cycle

Table 3.8, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for

each EEPROM operation.

3.9.2.2 MAC Address Reload

The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.

If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be

un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates

a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC

address.

3.9.2.3 EEPROM Command and Data Registers

Refer to Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 91 and Section 5.3.24,

"E2P_DATA – EEPROM Data Register," on page 93 for a detailed description of these registers.

Supported EEPROM operations are described in these sections.

3.9.2.4 EEPROM Timing

Refer to Section 6.9, "EEPROM Timing," on page 124 for detailed EEPROM timing specifications.

Table 3.8 Required EECLK Cycles

OPERATION REQUIRED EECLK CYCLES

ERASE 10

ERAL 10

EWDS 10

EWEN 10

WRITE 18

WRAL 18

EECLK

EEDIO (INPUT)

EEDIO (OUTPUT)

EECS

D7 D0

0 01

CSL