Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.5 (07-11-08) 20 SMSC LAN9118
DATASHEET
Note 2.1 Please refer to the SMSC application note AN 12.5 titled “Designing with the LAN9118 -
Getting Started”. It is also important to note that this application note applies to the whole
SMSC LAN9118 family of Ethernet controllers. However, subtle differences may apply.
3,65 Core Voltage
Decoupling
VDD_CORE P 2 1.8 V from internal core regulator.
Both pins must be connected
together externally and then tied to a
10uF 0.1-Ohm ESR capacitor, in
parallel with a 0.01uF capacitor to
Ground next to each pin. These pins
must not be used to supply power to
other external devices. See Note 2.1
1,66 Core Ground GND_CORE P 2 Ground for internal digital logic
7 PLL Power VDD_PLL P 1 1.8V Power from the internal PLL
regulator. This external pin must be
connected to a 10uF 0.1-Ohm ESR
capacitor, in parallel with a 0.01uF
capacitor to Ground. This pin must
not be used to supply power to other
external devices. See Note 2.1
4 PLL Ground VSS_PLL P 1 GND for the PLL
8 Reference Power VDD_REF P 1 Connected to 3.3v power and used
as the reference voltage for the
internal PLL
11 Reference Ground VSS_REF P 1 Ground for internal PLL reference
voltage
Table 2.5 System and Power Signals (continued)
PIN
NO.
NAME SYMBOL
BUFFER
TYPE
NUM
PINS
DESCRIPTION