Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118 17 Revision 1.5 (07-11-08)
DATASHEET
69 EEPROM Clock,
GPO4 RX_DV,
RX_CLK
EECLK/GPO4/
RX_DV/RX_CLK
O8 1 EEPROM Clock: Serial EEPROM
Clock pin.
General Purpose Output 4: This
pin can also function as a general-
purpose output, or it can be
configured to monitor the RX_DV or
RX_CLK signals on the internal MII
port. When configured as a GPO
signal, or as an RX_DV/RX_CLK
monitor, the EECS pin is deasserted
so as to never unintentionally access
the serial EEPROM. This signal
cannot function as a general-
purpose input.
Note: When the EEPROM
interface is not used, the
EECLK pin must be left
unconnected.
Table 2.5 System and Power Signals
PIN
NO.
NAME SYMBOL
BUFFER
TYPE
NUM
PINS
DESCRIPTION
6 Crystal 1 XTAL1 lclk 1 External 25MHz Crystal Input.
Can also be connected to single-
ended TTL oscillator. If this method is
implemented, XTAL2 should be left
unconnected.
5 Crystal 2 XTAL2 Oclk 1 External 25MHz Crystal output.
95 Reset nRESET IS
(PU)
1 Active-low reset input. Resets all logic
and registers within the LAN9118
This signal is pulled high with a weak
internal pull-up resistor. If nRESET is
left unconnected, the LAN9118 will
rely on its internal power-on reset
circuitry
Note: The LAN9118 must always
be read at least once after
power-up, reset, or upon
return from a power-saving
state or write operations will
not function. See Section
3.11, "Detailed Reset
Description," on page 41 for
additional information
Table 2.4 Serial EEPROM Interface Signals (continued)
PIN
NO. NAME SYMBOL
BUFFER
TYPE
NUM
PINS DESCRIPTION