Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118 15 Revision 1.5 (07-11-08)
DATASHEET
Table 2.1 Host Bus Interface Signals
PIN NO. NAME SYMBOL
BUFFER
TYPE
#
PINS DESCRIPTION
21-26,29-
33,36-40
Host Data High D[31:16] I/O8 (PD) 16 Bi-directional data port.
Note that Pull-down’s are disabled in
32 bit mode.
43-46,49-
53,56-59,62-
64
Host Data Low D[15:0] I/O8 16 Bi-directional data port.
12-18 Host Address A[7:1] IS 7 7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
92 Read Strobe nRD IS 1 Active low strobe to indicate a read
cycle.
93 Write Strobe nWR IS 1 Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9118
when it is in a reduced power state.
94 Chip Select nCS IS 1 Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9118 when it is in a
reduced power state.
72 Interrupt
Request
IRQ O8/OD8 1 Programmable Interrupt request.
Programmable polarity, source and
buffer types.
76 FIFO Select FIFO_SEL IS 1 When driven high all accesses to the
LAN9118 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
Table 2.2 Default Ethernet Settings
DEFAULT ETHERNET SETTINGS
SPEED_SEL SPEED DUPLEX AUTO NEG.
0 10MBPS HALF-DUPLEX DISABLED
1 100MBPS HALF-DUPLEX ENABLED