Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.5 (07-11-08) 122 SMSC LAN9118
DATASHEET
6.7 TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9118 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9118. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-
bit write. Note that address lines A[2:1] are still used when the LAN9118 is operating in 32-bit and 16-
bit mode. Address bits A[7:3] are ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Table 6.8 TX Data FIFO Direct PIO Write Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
cycle
Write Cycle Time 45 ns
t
csl
nCS, nWR Assertion Time 32 ns
t
csh
nCS, nWR Deassertion Time 13 ns
t
asu
Address, FIFO_SEL Setup to nCS, nWR Assertion 0 ns
t
ah
Address, FIFO_SEL Hold Time 0 ns
t
dsu
Data Setup to nCS, nWR Deassertion 7 ns
t
dh
Data Hold Time 0 ns
Data Bus
nCS, nWR
FIFO
_
SEL
A
[
2:1
]