Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118 121 Revision 1.5 (07-11-08)
DATASHEET
6.6 PIO Writes
PIO writes are used for all LAN9118 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are
identical with the exception that D[31:16] are ignored during a 16-bit write.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
cycle
Write Cycle Time 45 ns
t
csl
nCS, nWR Assertion Time 32 ns
t
csh
nCS, nWR Deassertion Time 13 ns
t
asu
Address Setup to nCS, nWR Assertion 0 ns
t
ah
Address Hold Time 0 ns
t
dsu
Data Setup to nCS, nWR Deassertion 7 ns
t
dh
Data Hold Time 0 ns
Data Bus
nCS, nWR
A
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