Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.5 (07-11-08) 120 SMSC LAN9118
DATASHEET
6.5 RX Data FIFO Direct PIO Burst Reads
In this mode the upper address inputs are not decoded, and any burst read of the LAN9118 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9118. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines. In this mode, performance is improved by allowing an unlimited number of back-to-back
DWORD or WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip
Select (nCS) or Read Enable (nRD). When either or both of these control signals go high, they must
remain high for the period specified.
Timing for 16-bit and 32-bit RX Data FIFO Direct PIO Burst Reads is identical with the exception that
D[31:16] are not driven during a 16-bit burst. Note that address lines A[2:1] are still used, and address
bits A[7:3] are ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
csh
nCS, nRD Deassertion Time 13 ns
t
csdv
nCS, nRD Valid to Data Valid 30 ns
t
acyc
Address Cycle Time 45
t
asu
Address, FIFO_SEL Setup to nCS, nRD Valid 0 ns
t
adv
Address Stable to Data Valid 40
t
ah
Address, FIFO_SEL Hold Time 0 ns
t
don
Data Buffer Turn On Time 0 ns
t
doff
Data Buffer Turn Off Time 7 ns
t
doh
Data Output Hold Time 0 ns
Data Bus
nCS, nRD
FIFO
_
SEL
A
[2:1]