Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.5 (07-11-08) 118 SMSC LAN9118
DATASHEET
6.3 PIO Burst Reads
In this mode, performance is improved by allowing up to 8, DWORD read cycles, or 16, WORD read
cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). Either or both of these control signals must go high between bursts for the period specified.
Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16]
are not driven during a 16-bit burst.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.2 LAN9118 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
csh
nCS, nRD Deassertion Time 13 ns
t
csdv
nCS, nRD Valid to Data Valid 30 ns
t
acyc
Address Cycle Time 45
t
asu
Address Setup to nCS, nRD valid 0 ns
t
adv
Address Stable to Data Valid 40
t
ah
Address Hold Time 0 ns
t
don
Data Buffer Turn On Time 0 ns
t
doff
Data Buffer Turn Off Time 7 ns
t
doh
Data Output Hold Time 0 ns
Data Bus
nCS, nRD
A[
7:5
]
A[
4:1
]