Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118 117 Revision 1.5 (07-11-08)
DATASHEET
6.2 PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles
is identical with the exception that D[31:16] are not driven during a 16-bit read.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 6.1 LAN9118 PIO Read Cycle Timing
Table 6.3 PIO Read Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
cycle
Read Cycle Time 45 ns
t
csl
nCS, nRD Assertion Time 32 ns
t
csh
nCS, nRD Deassertion Time 13 ns
t
csdv
nCS, nRD Valid to Data Valid 30 ns
t
asu
Address Setup to nCS, nRD Valid 0 ns
t
ah
Address Hold Time 0 ns
t
don
Data Buffer Turn On Time 0 ns
t
doff
Data Buffer Turn Off Time 7 ns
t
doh
Data Output Hold Time 0 ns
Data Bus
nCS, nRD
A[
7:1
]