Datasheet

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118 115 Revision 1.5 (07-11-08)
DATASHEET
Table 6.1 Read After Write Timing Rules
REGISTER NAME
MINIMUM WAIT TIME FOR READ
FOLLOWING ANY WRITE CYCLE
(IN NS)
NUMBER OF BYTE_TEST
READS
(ASSUMING T
CYCLE
OF 45NS)
ID_REV 0 0
IRQ_CFG 135 3
INT_STS 90 2
INT_EN 45 1
BYTE_TEST 0 0
FIFO_INT 45 1
RX_CFG 45 1
TX_CFG 45 1
HW_CFG 45 1
RX_DP_CTRL 45 1
RX_FIFO_INF 0 0
TX_FIFO_INF 135 3
PMT_CTRL 315 7
GPIO_CFG 45 1
GPT_CFG 45 1
GPT_CNT 135 3
WORD_SWAP 45 1
FREE_RUN 180 4
RX_DROP 0 0
MAC_CSR_CMD 45 1
MAC_CSR_DATA 45 1
AFC_CFG 45 1
E2P_CMD 45 1
E2P_DATA 45 1