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SMSC LAN9118 DATASHEET Revision 1.5 (07-11-08)

Datasheet

PRODUCT FEATURES

LAN9118

High Performance

Single-Chip 10/100 Non-

PCI Ethernet Controller

Highlights

 Optimized for the highest data-rate applications such

as high-definition video and multi-media applications

 Efficient architecture with low CPU overhead

 Easily interfaces to most 32-bit and 16-bit embedded

CPU’s

 Integrated PHY

 Supports audio & video streaming over Ethernet:

multiple high-definition (HD) MPEG2 streams

 Pin compatible with other members of LAN9118

family (LAN9117, LAN9116 and LAN9115)

Target Applications

 Video distribution systems, multi-room PVR

 High-end Cable, satellite, and IP set-top boxes

 Digital video recorders

 High definition televisions

 Digital media clients/servers

 Home gateways

Key Benefits

 Supports highest performance applications

— Highest performing non-PCI Ethernet controller in the

market

— 32-bit interface with fast bus cycle times

— Burst-mode read support

 Eliminates dropped packets

— Internal buffer memory can store over 200 packets

— Supports automatic or host-triggered PAUSE and back-

pressure flow control

 Minimizes CPU overhead

— Supports Slave-DMA

— Interrupt Pin with Programmable Hold-off timer

 Reduces system cost and increases design flexibility

— SRAM-like interface easily interfaces to most

embedded CPU’s or SoC’s

— Low-cost, low--pin count non-PCI interface for

embedded designs

 Reduced Power Modes

— Numerous power management modes

— Wake on LAN*

— Magic packet wakeup*

— Wakeup indicator event signal

— Link Status Change

 Single chip Ethernet controller

— Fully compliant with IEEE 802.3/802.3u standards

— Integrated Ethernet MAC and PHY

— 10BASE-T and 100BASE-TX support

— Full- and Half-duplex support

— Full-duplex flow control

— Backpressure for half-duplex flow control

— Preamble generation and removal

— Automatic 32-bit CRC generation and checking

— Automatic payload padding and pad removal

— Loop-back modes

 Flexible address filtering modes

— One 48-bit perfect address

— 64 hash-filtered multicast addresses

— Pass all multicast

— Promiscuous mode

— Inverse filtering

— Pass all incoming with status report

— Disable reception of broadcast packets

 Integrated Ethernet PHY

— Auto-negotiation

— Automatic polarity detection and correction

 High-Performance host bus interface

— Simple, SRAM-like interface

— 32/16-bit data bus

— Large, 16Kbyte FIFO memory that can be allocated to

RX or TX functions

— One configurable host interrupt

 Miscellaneous features

— Low profile 100-pin, TQFP lead-free RoHS Compliant

package

— Integral 1.8V regulator

— General Purpose Timer

— Support for optional EEPROM

— Support for 3 status LEDs multiplexed with

Programmable GPIO signals

 3.3V Power Supply with 5V tolerant I/O

 0 to 70°C

* Third-party brands and names are the property of their respective

owners.

Summary of content (132 pages)

PAGE 1
LAN9118 High Performance Single-Chip 10/100 NonPCI Ethernet Controller PRODUCT FEATURES Datasheet Highlights Optimized for the highest data-rate applications such as high-definition video and multi-media applications Efficient architecture with low CPU overhead Easily interfaces to most 32-bit and 16-bit embedded CPU’s Integrated PHY Supports audio & video streaming over Ethernet: multiple high-definition (HD) MPEG2 streams Pin compatible with other members of LAN9118 family (LAN9117,
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet ORDER NUMBER: LAN9118-MT FOR 100 PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table of Contents Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.13 3.12.6 Transmit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.7 Transmitter Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.8 Stopping and Starting the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Data Path Operation . . . . . . . . . .
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4 5.5 5.3.11 RX_FIFO_INF—Receive FIFO Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.12 TX_FIFO_INF—Transmit FIFO Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3.13 PMT_CTRL— Power Management Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.14 GPIO_CFG—General Purpose IO Configuration Register . . . . . . . . . . . . . . . . . . . .
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 7 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet List of Figures Figure 1.1 Figure 1.2 Figure 2.1 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Figure 3.16 Figure 3.17 Figure 3.18 Figure 4.1 Figure 4.2 Figure 5.1 Figure 5.2 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 8.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet List of Tables Table 2.1 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2.2 Default Ethernet Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2.3 LAN Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 1 General Description The LAN9118 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9118 has been specifically architected to provide the highest performance possible for any given architecture. The LAN9118 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet System Memory System Memory System Peripherals Magnetics Microprocessor/ Microcontroller System Bus Ethernet LAN9118 LEDS/GPIO 25MHz XTAL EEPROM (Optional) Figure 1.1 System Block Diagram Utilizing the SMSC LAN9118 The SMSC LAN9118 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 1.1 Internal Block Overview This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal Block Diagram". 25MHz +3.3V PME Wakup Indicator Power Management Host Bus Interface (HBI) SRAM I/F 3.3V to 1.8V Core Regulator Interrupt Controller 3.3V to 1.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and will queue an entire frame before beginning transmission. 1.4 Receive and Transmit FIFOs The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between the host interface and the MAC through which all transmitted and received data and status information is passed.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet The LAN9118 host bus interface supports 32-bit and 16-bit bus transfers; internally, all data paths are 32-bits wide. The LAN9118 can be interfaced to either Big-Endian or Little-Endian processors in either 32-bit or 16-bit external bus width modes of operation. The host bus data Interface is responsible for host address decoding and data bus steering.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC SPEED_SEL NC IRQ NC PME EECLK** EECS EEDIO** GND_CORE VDD_CORE D0 D1 D2 VDD_IO GND_IO D3 D4 D5 D6 VDD_IO GND_IO D7 D8 D9 Chapter 2 Pin Description and Configuration FIFO_SEL VSS_A TPO- 76 TPO+ VSS_A VDD_A 79 80 81 82 TPITPI+ NC VDD_A VSS_A EXRES1 VSS_A VDD_A NC*2 NC*1 nRD nWR nCS nRESET GND_IO VDD_IO GPIO0/nLED1** 83 84 85 86 87 88 89 90 91 92 93 S
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.1 Host Bus Interface Signals PIN NO. NAME SYMBOL BUFFER TYPE # PINS 21-26,2933,36-40 Host Data High D[31:16] I/O8 (PD) 16 Bi-directional data port. Note that Pull-down’s are disabled in 32 bit mode. 43-46,4953,56-59,6264 Host Data Low D[15:0] I/O8 16 Bi-directional data port. 12-18 Host Address A[7:1] IS 7 7-bit Address Port. Used to select Internal CSR’s and TX and RX FIFOs.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.3 LAN Interface Signals PIN NO. NAME SYMBOL BUFFER TYPE NUM PINS 79 TXP TPO+ AO 1 Twisted Pair Transmit Output, Positive 78 TXN TPO- AO 1 Twisted Pair Transmit Output, Negative 83 RXP TPI+ AI 1 Twisted Pair Receive Input, Positive 82 RXN TPI- AI 1 Twisted Pair Receive Input, Negative 87 PHY External Bias Resistor EXRES1 AI 1 Must be connected to ground through a 12.4K ohm 1% resistor.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.4 Serial EEPROM Interface Signals (continued) PIN NO. 69 NAME SYMBOL EEPROM Clock, GPO4 RX_DV, RX_CLK EECLK/GPO4/ RX_DV/RX_CLK BUFFER TYPE NUM PINS O8 1 DESCRIPTION EEPROM Clock: Serial EEPROM Clock pin. General Purpose Output 4: This pin can also function as a generalpurpose output, or it can be configured to monitor the RX_DV or RX_CLK signals on the internal MII port.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.5 System and Power Signals (continued) PIN NO. 70 NAME Wakeup Indicator SYMBOL PME BUFFER TYPE NUM PINS O8/OD8 1 DESCRIPTION When programmed to do so, is asserted when the LAN9118 detects a wake event and is requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.5 System and Power Signals (continued) PIN NO. 100, 99, 98 NAME General Purpose I/O data, nLED1 (Speed Indicator), nLED2 (Link & Activity Indicator), SYMBOL GPIO[2:0]/ LED[3:1] BUFFER TYPE NUM PINS IS/O12/ OD12 3 nLED3 (FullDuplex Indicator).
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.5 System and Power Signals (continued) PIN NO. NAME SYMBOL BUFFER TYPE NUM PINS DESCRIPTION 3,65 Core Voltage Decoupling VDD_CORE P 2 1.8 V from internal core regulator. Both pins must be connected together externally and then tied to a 10uF 0.1-Ohm ESR capacitor, in parallel with a 0.01uF capacitor to Ground next to each pin. These pins must not be used to supply power to other external devices. See Note 2.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 2.1 Buffer Types Table 2.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 3 Functional Description 3.1 10/100 Ethernet MAC The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-compliant node and provides an interface between the host subsystem and the internal Ethernet PHY. The MAC can operate in either 100-Mbps or 10-Mbps mode. The MAC operates in both half-duplex and full-duplex modes.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.2 Flow Control The LAN9118 Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also supports half-duplex flow control using back pressure. 3.2.1 Full-Duplex Flow Control The pause operation inhibits data transmission of data frames for a specified period of time.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Network efficiency: Allows shielding one system resource from traffic not meant for that resource. A workstation in one VLAN is shielded from traffic on another VLAN, increasing that workstation’s efficiency. Broadcast containment: Leakage of broadcast frames from one VLAN to another is prevented.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Figure 3.2 VLAN Frame The MAC Function recognizes transmitted and received frames tagged with either one-level or twolevel VLAN IDs. The MAC compares the thirteenth and fourteenth bytes of transmit and receive frames to the contents of both the one-level VLAN tag register and the two-level VLAN tag register.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.3 Address Filtering Functional Description The Ethernet address fields of an Ethernet Packet, consists of two 6-byte fields: one for the destination address and one for the source address. The first bit of the destination address signifies whether it is a physical address or a multicast address. The LAN9118 address check logic filters the frame based on the Ethernet receive filter mode that has been enabled.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.4.2.1 Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9118 Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9118 packet filter function performs an imperfect address filtering against the hash table.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Note 3.3 When wake-up frame detection is enabled via the WUEN bit of the WUCSR—Wake-up Control and Status Register, a broadcast wake-up frame will wake-up the device despite the state of the Disable Broadcast Frames (BCAST) bit in the MAC_CR—MAC Control Register. Table 3.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 3.5 Filter i Offset Bit Definitions FILTER I OFFSET DESCRIPTION FIELD DESCRIPTION 7:0 Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame recognition. The minimum value of this field must be 12 since there should be no CRC check for the destination address and the source address fields.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Destination Address Source Address ……………FF FF FF FF FF FF 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC It should be noted that Magic Packet detection can be performed when LAN9118 is in the
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Additionally, please refer to Section 5.3.17, "WORD_SWAP—Word Swap Control," on page 86 for additional information on status indication on Endian modes. Table 3.7 Byte Lane Mapping DATA PINS MODE OF OPERATION 32-bit D[31:24] D[23:16] D[15:8] D[7:0] DESCRIPTION Byte 3 (MSB) Byte 2 Byte 1 Byte 0 (LSB) This is the native mode of the LAN9118. Endianess does not matter when both WORD lanes are in operation.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.9.1 MAC Address Auto-Load On power-up, hard reset or soft reset, the EEPROM controller attempts to read the first byte of data from the EEPROM (address 00h). If the value A5h is read from the first address, then the EEPROM controller will assume that an external Serial EEPROM is present. The EEPROM controller will then access the next EEPROM byte and send it to the MAC Address register byte 0 (ADDRL[7:0]).
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet EEPROM Write EEPROM Read Idle Idle Write Data Register Write Command Register Write Command Register Read Command Register Busy Bit = 0 Busy Bit = 0 Read Command Register Read Data Register Figure 3.3 EEPROM Access Flow Diagram The host can disable the EEPROM interface through the GPIO_CFG register.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet tCSL EECS EECLK EEDIO (OUTPUT) 1 1 1 A6 A0 EEDIO (INPUT) Figure 3.4 EEPROM ERASE Cycle ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 1 0 EEDIO (INPUT) Figure 3.5 EEPROM ERAL Cycle Revision 1.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 0 0 EEDIO (INPUT) Figure 3.6 EEPROM EWDS Cycle EWEN (Erase/Write Enable): Enables the EEPROM for erase and write operations.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address (EPC_ADDR). The result of the read is available in the E2P_DATA register. tCSL EECS EECLK EEDIO (OUTPUT) 1 1 0 A6 A0 EEDIO (INPUT) D7 D0 Figure 3.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not respond within 30ms. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 0 D7 1 D0 EEDIO (INPUT) Figure 3.10 EEPROM WRAL Cycle Table 3.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.10 Power Management LAN9118 supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.10.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.9, “Power Management States,” on page 39. All configuration data is saved when in either of the two low power states.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Note 3.8 The host must do only read accesses prior to the ready bit being set. Once the READY bit is set, the LAN9118 is ready to resume normal operation. At this time the WUPS field can be cleared. 3.10.2.2 D2 Sleep In this state, as shown in Table 3.9, all clocks to the MAC and host bus are disabled, and the PHY is placed in a reduced power state.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.10.2.3 Power Managment Event Indicators Figure 3.11 is a simplified block diagram of the logic that controls the external PME, and internal pme_interrupt signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS register, which, if enabled, will generate a host interrupt upon detection of a power management event.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.10.3.2 Energy Detect Power-Down This power-down mode is activated by setting the Phy register bit 17.13 to 1. Please refer to Section 5.5.8, "Mode Control/Status," on page 110 for additional information on this register. In this mode when no energy is present on the line, the PHY is powered down, with th exception of the management interface, the SQUELCH circuit and the ENERGYON logic.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.11.1 Power-On Reset (POR) A Power-On reset occurs whenever power is initially applied to the LAN9118, or if power is removed and reapplied to the LAN9118. A timer within the LAN9118 will assert the internal reset for approximately 22ms. The READY bit in the PMT_CTRL register can be read from the host interface and will read back a ‘0’ until the POR is complete.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12 TX Data Path Operation Data is queued for transmission by writing it into the TX data FIFO. Each packet to be transmitted may be divided among multiple buffers. Each buffer starts with a two DWORD TX command (TX command ‘A’ and TX command ‘B’). The TX command instructs the LAN9118 on the handling of the associated buffer. Packet boundaries are delineated using control bits within the TX command.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet init Idle TX Status Available Check available FIFO space Read TX Status (optional) Write TX Command Write Start Padding (optional) Last Buffer in Packet Not Last Buffer Write Buffer Figure 3.12 Simplified Host TX Flow Diagram Revision 1.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12.1 TX Buffer Format TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32bit values that are used by the LAN9118 in the handling and processing of the associated Ethernet packet data buffer.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do not match, the Ethernet controller will assert the Transmitter Error (TXE) flag. TX COMMAND ‘A’ Table 3.11 TX Command 'A' Format BITS DESCRIPTION 31 Interrupt on Completion.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet TX COMMAND ‘B’ Table 3.12 TX Command 'B' Format BITS DESCRIPTION 31:16 Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to the corresponding TX status word and can be used by the host to correlate TX status words with their corresponding packets. Note: 15:14 The use of packet tags is not required by the hardware.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet The MIL operates in store-and-forward mode and has specific rules with respect to fragmented packets. The total space consumed in the TX FIFO (MIL) must be limited to no more than 2KB - 3 DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a Driver-supplied buffer) before the transmit packet can be sent to the LAN9118.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 7 DESCRIPTION Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility. 6:3 Collision Count. This counter indicates the number of collisions that occurred before the packet was transmitted. It is not valid when excessive collisions (bit 8) is also set. 2 Excessive Deferral.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Data W ritten to the Ethernet Controller 31 TX Com m and 'A' Buff er End Alignment = 1 Data Start Of fset = 7 First Segment = 1 Last Segment = 0 Buff er Size = 79 0 TX Command 'A' Data Passed to the TX Data FIFO TX Command 'B' 7-Byte Data Start Offset TX Command 'A' TX Com m and 'B' Packet Length = 111 TX Command 'B' 79-Byte Payload 79-Byte Payload Pad DW ORD 1 10-Byte End Padding TX Command 'A' 31 TX Com m and 'A' Buff er E
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12.6.2 TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet is in a single buffer as follows: 2-Byte “Data Start Offset” 183-Bytes of payload data 4-Byte “Buffer End Alignment” Figure 3.15, "TX Example 2" illustrates the TX command structure for this example, and also shows how data is passed to the TX data FIFO.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12.7 Transmitter Errors If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation. TX Error (TXE) will be asserted under the following conditions: 3.12.8 If the actual packet length count does not match the Packet Length field as defined in the TX command. Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.13.1 RX Slave PIO Operation Using PIO mode, the host can either implement a polling or interrupt scheme to empty the received packet out of the RX data FIFO. The host will remain in the idle state until it receives an indication (interrupt or polling) that data is available in the RX data FIFO.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.13.1.1 Receive Data FIFO Fast Forward The RX data path implements an automatic data discard function. Using the RX data FIFO Fast Forward bit (RX_FFWD) in the RX_DP_CTRL register, the host can instruct the LAN9118 to skip the packet at the head of the RX data FIFO. The RX data FIFO pointers are automatically incremented to the beginning of the next RX packet.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Host Read Order 31 0 1st Optional offset DWORD0 2nd . . Optional offset DWORDn ofs + First Data DWORD . . . . Last Data DWORD Optional Pad DWORD0 . . Last Optional Pad DWORDn Figure 3.18 RX Packet Format 3.13.3 RX Status Format BITS DESCRIPTION 31 Reserved. This bit is reserved. Reads 0. 30 Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing filtering.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 9:8 DESCRIPTION Reserved. These bits are reserved. Reads 0. 7 Frame Too Long. When set, this bit indicates that the frame length exceeds the maximum Ethernet specification of 1518 bytes. This is only a frame too long indication and will not cause the frame reception to be truncated. 6 Collision Seen. When set, this bit indicates that the frame has seen a collision after the collision window.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 4 Internal Ethernet PHY 4.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 4.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 4.1 4B/5B Code Table (continued) CODE GROUP SYM 01000 V INVALID, RX_ER if during RX_DV INVALID 01100 V INVALID, RX_ER if during RX_DV INVALID 10000 V INVALID, RX_ER if during RX_DV INVALID 4.2.2 RECEIVER INTERPRETATION TRANSMITTER INTERPRETATION Scrambling Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band peaks.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 100M PLL RX_CLK MAC Internal MII 25MHz by 4 bits 25MHz by 4 bits MII 4B/5B Decoder 25MHz by 5 bits Descrambler and SIPO 125 Mbps Serial NRZI Converter A/D Converter NRZI MLT-3 MLT-3 Converter DSP: Timing recovery, Equalizer and BLW Correction MLT-3 Magnetics MLT-3 RJ45 MLT-3 CAT-5 6 bit Data Figure 4.2 Receive Data Path 4.3 100Base-TX Receive The receive data path is shown in Figure 4.2.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet (TX_EN is low), the TX10M block outputs Normal Link Pulses (NLPs) to maintain communications with the remote link partner. 4.4.3 10M Transmit Drivers The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out as a differential signal across the TXP and TXN outputs. 4.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the internal Serial Management Interface (SMI). The results of the negotiation process are reflected in the Speed Indication bits in register 31, as well as the Link Partner Ability Register (Register 5). The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN9118 does not support “Next Page" capability. 4.7 Parallel Detection If the LAN9118 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 4.2 CRS Behavior MODE SPEED DUPLEX ACTIVITY CRS BEHAVIOR (Note 4.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 5 Register Description The following section describes all LAN9118 registers and data ports. FCh RESERVED B4h EEPROM Port B0h ACh A8h A4h A0h 50h 4Ch 48h 44h 40h 3Ch MAC CSRPort TX Status TX Status RX Status RX Status FIFO PEEK FIFO Port FIFO PEEK FIFO Port TX Data FIFO Alias Ports 24h 20h 1Ch TX Data FIFO Port RX Data FIFO Alias Ports 04h Base + 00h RX Data FIFO Port Figure 5.1 LAN9118 Memory Map Revision 1.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.1 Register Nomenclature and Access Attributes SYMBOL DESCRIPTION RO Read Only: If a register is read only, writes to this register have no effect. WO Write Only: If a register is write only, reads always return 0. R/W Read/Write: A register with this attribute can be read and written R/WC Read/Write Clear: A register bit with this attribute can be read and written.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.2.2 TX FIFO Ports The TX data Path consists of two FIFOs, the TX status and data. The TX Status FIFO can be read from two locations. The TX Status FIFO Port will perform a destructive read, thus “Popping” the data from the TX Status FIFO. There is also the TX Status FIFO PEEK location. This location allows a nondestructive read of the top (oldest) location of the FIFO. The TX data FIFO is Write Only.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.2 IRQ_CFG—Interrupt Configuration Register Offset: 54h Size: 32 bits This register configures and indicates the state of the IRQ signal. BITS 31:24 DESCRIPTION TYPE Interrupt Deassertion Interval (INT_DEAS). This field determines the Interrupt Deassertion Interval for the Interrupt Request in multiples of 10 microseconds. DEFAULT R/W 0 Reserved RO - 14 Interrupt Deassertion Interval Clear (INT_DEAS_CLR).
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.3 INT_STS—Interrupt Status Register Offset: 58h Size: 32 bits This register contains the current status of the generated interrupts. Writing a 1 to the corresponding bits acknowledges and clears the interrupt. BITS 31 30-26 DESCRIPTION Software Interrupt (SW_INT). This interrupt is generated when the SW_INT_EN bit is set high. Writing a one clears this interrupt.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 12-11 DESCRIPTION Reserved TYPE DEFAULT RO - 10 TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data FIFO is full, and another write is attempted. R/WC 0 9 TX Data FIFO Available Interrupt (TDFA). Generated when the TX data FIFO available space is greater than the programmed level. R/WC 0 8 TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status FIFO is full.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.4 INT_EN—Interrupt Enable Register Offset: 5Ch Size: 32 bits This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.5 BYTE_TEST—Byte Order Test Register Offset: 64h Size: 32 bits This register can be used to determine the byte ordering of the current configuration BITS DESCRIPTION 31:0 Byte Test 5.3.6 TYPE DEFAULT RO 87654321h FIFO_INT—FIFO Level Interrupts Offset: 68h Size: 32 bits This register configures the limits where the FIFO Controllers will generate system interrupts.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.7 RX_CFG—Receive Configuration Register Offset: 6Ch Size: 32 bits This register controls the LAN9118 receive engine. BITS DESCRIPTION TYPE DEFAULT 31:30 RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9118 will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.8 TX_CFG—Transmit Configuration Register Offset: 70h Size: 32 bits This register controls the transmit functions on the LAN9118 Ethernet Controller. BITS DESCRIPTION TYPE DEFAULT 31-16 Reserved. RO - 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.9 HW_CFG—Hardware Configuration Register Offset: 74h Size: 32 bits This register controls the hardware configuration of the LAN9118 Ethernet Controller. Note: The transmitter and receiver must be stopped before writing to this register. Refer to Section 3.12.8, "Stopping and Starting the Transmitter," on page 52 and Section 3.13.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet configuration (HW_CFG) register. The TX_FIF_SZ field selects the total allocation for the TX data path, including the TX Status FIFO size. The TX Status FIFO size is fixed at 512 Bytes (128 TX Status DWORDs). The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder being the TX data FIFO Size. Note that TX data FIFO space includes both commands and payload data.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO. Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9118, it is moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.10 RX_DP_CTRL—Receive Datapath Control Register Offset: 78h Size: 32 bits This register is used to discard unwanted receive frames. BITS 31 DESCRIPTION TYPE DEFAULT RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes the RX data FIFO to fast-forward to the start of the next frame. This bit will remain high until the RX data FIFO fast-forward operation has completed.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.12 TX_FIFO_INF—Transmit FIFO Information Register Offset: 80h Size: 32 bits This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the LAN9118. BITS DESCRIPTION TYPE DEFAULT 31-24 Reserved RO - 23-16 TX Status FIFO Used Space (TXSUSED). Indicates the amount of space in DWORDS used in the TX Status FIFO. RO 00h 15-0 TX Data FIFO Free Space (TDFREE).
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.13 PMT_CTRL— Power Management Control Register Offset: 84h Size: 32 bits This register controls the Power Management features. This register can be read while the LAN9118 is in a power saving mode. Note: The LAN9118 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 5-4 DESCRIPTION TYPE WAKE-UP Status (WUPS) – This field indicates the cause of a wake-up event detection as follows DEFAULT R/WC 00 R/W 0b 00b -- No wake-up event detected 01b -- Energy detected 10b -- Wake-up frame or magic packet detected 11b -- Indicates multiple events occurred WUPS bits are cleared by writing a ‘1’ to the appropriate bit.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.14 GPIO_CFG—General Purpose IO Configuration Register Offset: 88h Size: 32 bits This register configures the GPIO and LED functions. Bits Type Default Reserved RO - LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output. When cleared low, the pin functions as a GPIO signal.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Bits Description Type Default 4:3 GPO Data 3-4 (GPODn). The value written is reflected on GPOn. GPO3 – bit 3 GPO4 – bit 4 R/W 00 2:0 GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is reflected on GPIOn. When read, GPIOn reflects the current state of the corresponding GPIO pin. GPIO0 – bit 0 GPIO1 – bit 1 GPIO2 – bit 2 R/W 000 Table 5.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.16 GPT_CNT-General Purpose Timer Current Count Register Offset: 90h Size: 32 bits This register reflects the current value of the GP Timer. BITS DESCRIPTION 31-16 15-0 5.3.17 TYPE DEFAULT Reserved RO - General Purpose Timer Current Count (GPT_CNT). This 16-bit field reflects the current value of the GP Timer.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.18 FREE_RUN—Free-Run 25MHz Counter Offset: 9Ch Size: 32 bits This register reflects the value of the free-running 25MHz counter. BITS DESCRIPTION 31:0 Free Running SCLK Counter (FR_CNT): 5.3.19 Note: This field reflects the value of a free-running 32-bit counter. At reset the counter starts at zero and is incremented for every 25MHz cycle. When the maximum count has been reached the counter will rollover.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register Offset: A4h Size: 32 bits This register is used to control the read and write operations with the MAC CSR’s BITS DESCRIPTION TYPE DEFAULT 31 CSR Busy. When a 1 is written into this bit, the read or write operation is performed to the specified MAC CSR. This bit will remain set until the operation is complete.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.22 AFC_CFG – Automatic Flow Control Configuration Register Offset: ACh Size: 32 bits This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9118 will not transmit pause frames or assert back pressure if the transmitter is disabled.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 0 DESCRIPTION TYPE DEFAULT Flow Control on Any Frame (FCANY). When this bit is set, the LAN9118 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9118 is operating in full-duplex mode.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.23 E2P_CMD – EEPROM Command Register Offset: B0h Size: 32 bits This register is used to control the read and write operations with the Serial EEPROM. BITS 31 DESCRIPTION EPC Busy: When a 1 is written into this bit, the operation specified in the EPC command field is performed at the specified EEPROM address. This bit will remain set until the operation is complete.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS DESCRIPTION TYPE DEFAULT 30-28 EPC command. This field is used to issue commands to the EEPROM controller. The EPC will execute commands when the EPC Busy bit is set. A new command must not be issued until the previous command completes.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 9 DESCRIPTION TYPE DEFAULT EPC Time-out. If an EEPROM operation is performed, and there is no R/WC 0 RO - R/W 00h response from the EEPROM within 30mS, the EEPROM controller will timeout and return to its idle state. This bit is set when a time-out occurs indicating that the last operation was unsuccessful.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4 MAC Control and Status Registers These registers are located in the MAC module and are accessed indirectly through the MAC-CSR synchronizer port. Table 5.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.1 MAC_CR—MAC Control Register Offset: 1 Attribute: R/W Default Value: 00040000h Size: 32 bits This register establishes the RX and TX operation modes and controls for address filtering and packet filtering. BITS DESCRIPTION 31 Receive All Mode (RXALL). When set, all incoming packets will be received and passed on to the address filtering Function for processing of the selected filtering mode on the received frame.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 13 DESCRIPTION Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9118 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS DESCRIPTION 5 Deferral Check (DFCHK). When set, enables the deferral check in the MAC. The MAC will abort the transmission attempt if it has deferred for more than 24,288 bit times. Deferral starts when the transmitter is ready to transmit, but is prevented from doing so because the CRS is active. Defer time is not cumulative.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.3 ADDRL—MAC Address Low Register Offset: 3 Attribute: R/W Default Value: FFFFFFFFh Size: 32 bits The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Controller if a programmed EEPROM is detected.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.4 HASHH—Multicast Hash Table High Register Offset: 4 Attribute: R/W Default Value: 00000000h Size: 32 bits The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the Hash table.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.6 MII_ACC—MII Access Register Offset: 6 Attribute: R/W Default Value: 00000000h Size: 32 bits This register is used to control the Management cycles to the PHY. BITS DESCRIPTION 31-16 Reserved 15-11 PHY Address: For every access to this register, this field must be set to 00001b. 10-6 MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.8 FLOW—Flow Control Register Offset: 8 Attribute: R/W Default Value: 00000000h Size: 32 bits This register controls the generation and reception of the Control (Pause command) frames by the MAC’s flow control block. The control frame fields are selected as specified in the 802.3x Specification and the Pause-Time value from this register is used in the “Pause Time” field of the control frame.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.9 VLAN1—VLAN1 Tag Register Offset: 9 Attribute: R/W Default Value: 00000000h Size: 32 bits This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame length is increased from 1518 bytes to 1522 bytes. BITS DESCRIPTION 31-16 Reserved 15-0 VLAN1 Tag Identifier (VTI1). This contains the VLAN Tag field to identify the VLAN1 frames.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.11 WUFF—Wake-up Frame Filter Offset: B Attribute: WO Default Value: 00000000h Size: 32 bits This register is used to configure the wake up frame filter. BITS DESCRIPTION 31-0 Wake-Up Frame Filter (WFF). Wake-Up Frame Filter (WFF). The Wake-up frame filter is configured through this register using an indexing mechanism.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5 PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers. PHY Register Indexes are shown in Table 5.8, "LAN9118 PHY Control and Status Register"below.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.1 Basic Control Register Index (In Decimal): BITS 0 Size: 16-bits DESCRIPTION TYPE DEFAULT RW/SC 0 15 Reset. 1 = software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits in this register. 14 Loopback. 1 = loopback mode, 0 = normal operation RW 0 13 Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is enabled (0.12 = 1). RW See Note 5.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.2 Basic Status Register Index (In Decimal): BITS 1 Size: 16-bits DESCRIPTION TYPE DEFAULT 15 100Base-T4. 1 = T4 able, 0 = no T4 ability RO 0 14 100Base-TX Full Duplex. 1 = TX with full duplex, 0 = no TX full duplex ability. RO 1 13 100Base-TX Half Duplex. 1 = TX with half duplex, 0 = no TX half duplex ability. RO 1 12 10Base-T Full Duplex.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.3 PHY Identifier 1 Index (In Decimal): 2 Size: BITS DESCRIPTION 15-0 PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. 5.5.4 16-bits TYPE DEFAULT RO 0x0007h TYPE DEFAULT 0xC0D1h PHY Identifier 2 Index (In Decimal): 3 Size: 16-bits BITS DESCRIPTION 15-10 PHY ID Number b. Assigned to the 19th through 24th bits of the OUI.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.5 Auto-negotiation Advertisement Index (In Decimal): BITS DESCRIPTION 15-14 4 Size: 16-bits TYPE DEFAULT Reserved RO 00 13 Remote Fault. 1 = remote fault detected, 0 = no remote fault R/W 0 12 Reserved R/W 0 Pause Operation. (See Note 5.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.6 Auto-negotiation Link Partner Ability Index (In Decimal): BITS 5 Size: 16-bits DESCRIPTION TYPE DEFAULT 15 Next Page. 1 = next page capable, 0 = no next page ability. This device does not support next page ability. RO 0 14 Acknowledge. 1 = link code word received from partner 0 = link code word not yet received RO 0 Note: This bit will always read 0 13 Remote Fault.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.7 Auto-negotiation Expansion Index (In Decimal): BITS DESCRIPTION 15:5 Reserved 6 Size: 16-bits TYPE DEFAULT RO 0 4 Parallel Detection Fault. 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic RO/LH 0 3 Link Partner Next Page Able. 1 = link partner has next page ability 0 = link partner does not have next page ability RO 0 2 Next Page Able.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.9 Special Modes Index (In Decimal): ADDRESS 18 Size: 16-bits DESCRIPTION TYPE DEFAULT 15-8 Reserved RW, NASR 7:5 MODE: PHY Mode of operation. Refer to Table 5.9 for more details. RW, NASR See Table 5.9 4:0 PHYAD: PHY Address: The PHY Address is used for the SMI address. RW, NASR 00001b Table 5.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.10 Special Control/Status Indications Index (In Decimal): ADDRESS 15:11 27 Size: 16-bits DESCRIPTION Reserved: Write as 0. Ignore on read. MODE DEFAULT RW 0 RW, NASR 0 10 VCOOFF_LP: Forces the Receive PLL 10M to lock on the reference clock at all times: 0 - Receive PLL 10M can lock on reference or line as needed (normal operation) 1 - Receive PLL 10M is locked on the reference clock.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.12 Interrupt Mask Index (In Decimal): BITS DESCRIPTION 15-8 7-0 30 Size: 16-bits TYPE DEFAULT Reserved. Write as 0; ignore on read. RO 0 Mask Bits. 1 = interrupt source is enabled 0 = interrupt source is masked RW 0 TYPE DEFAULT Reserved. RO 000b Autodone. Auto-negotiation done indication: 0 = Auto-negotiation is not done or disabled (or not active) 1 = Auto-negotiation is done RO 0b 11-5 Reserved.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 6 Timing Diagrams 6.1 Host Interface Timing The LAN9118 supports the following host cycles: Read Cycles: PIO Reads (nCS or nRD controlled) PIO Burst Reads (nCS or nRD controlled) RX Data FIFO Direct PIO Reads (nCS or nRD controlled) RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled) Write Cycles: 6.1.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 6.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.1.2 Special Restrictions on Back-to-Back Read Cycles There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9118, and the subsequent indication of the expected change in the control register values.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.2 PIO Reads PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between cycles for the period specified.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.3 PIO Burst Reads In this mode, performance is improved by allowing up to 8, DWORD read cycles, or 16, WORD read cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between bursts for the period specified.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.4 RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9118 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.5 RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9118 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.6 PIO Writes PIO writes are used for all LAN9118 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are identical with the exception that D[31:16] are ignored during a 16-bit write.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.7 TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9118 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.8 Reset Timing T6.1 nRST T6.2 T6.3 Configuration signals T6.4 Output drive Table 6.9 Reset Timing PARAMETER DESCRIPTION MIN TYP MAX UNITS T6.1 Reset Pulse Width 200 us T6.2 Configuration input setup to nRST rising 200 ns T6.3 Configuration input hold after nRST rising 10 ns T6.4 Output Drive after nRST rising SMSC LAN9118 16 123 DATASHEET NOTES ns Revision 1.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.9 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9118 Figure 6.7 EEPROM Timing Table 6.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 7 Operational Characteristics 7.1 Absolute Maximum Ratings* Supply Voltage (VDD_A, VDD_REF, VREG, VDD_IO) (Note 7.1) . . . . . . . . . . . . . . . .0V to +3.3V+10% Positive voltage on signal pins, with respect to ground (Note 7.2) . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Negative voltage on signal pins, with respect to ground (Note 7.3) . . . . . . . . . . . . . . . . . . . . . . . . -0.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 7.3 Power Consumption Device Only Power measurements taken under the following conditions: Temperature: .................................................................................................................................. +25° C Device VDD:..................................................................................................................................+3.30 V Table 7.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 7.4 Power Consumption Device and System Components This section describes typical power consumption values of a total Ethernet LAN connectivity solution, which includes external components supporting the SMSC Ethernet controller. The values below should be used as comparision measurements only for power provisioning.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 7.5 DC Electrical Specifications Table 7.3 I/O Buffer Characteristics PARAMETER SYMBOL MIN Low Input Level VILI High Input Level TYP MAX UNITS NOTES -0.3 0.8 V VIHI 2.0 5.5 V Negative-Going Threshold VILT 1.01 1.18 1.35 V Schmitt Trigger Positive-Going Threshold VIHT 1.39 1.6 1.8 V Schmitt Trigger Schmitt Trigger Hysteresis (VIHT - VILT) VHYS 345 420 485 mV 0.4 V IOL = 12mA V IOH = -12mA 0.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 7.4 100BASE-TX Tranceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Peak Differential Output Voltage High VPPH 950 - 1050 mVpk Note 7.7 Peak Differential Output Voltage Low VPPL -950 - -1050 mVpk Note 7.7 Signal Amplitude Symmetry VSS 98 - 102 % Note 7.7 Signal Rise & Fall Time TRF 3.0 - 5.0 nS Note 7.7 Rise & Fall Time Symmetry TRFS - - 0.5 nS Note 7.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 7.6 Clock Circuit The LAN9118 can accept either a 25MHz crystal (preferred) or a 25 MHz clock oscillator (±50 PPM) input. The LAN9118 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1 (pin 6). If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3.3V clock signal.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 8 Package Outline Figure 8.1 100 Pin TQFP Package Definition Table 8.1 100 Pin TQFP Package Parameters A A1 A2 D D1 E E1 H L L1 e q W R1 R2 ccc MIN ~ NOMINAL ~ MAX 1.60 REMARKS Overall Package Height 0.05 1.35 15.80 13.90 15.80 13.90 0.09 0.45 ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.50 Basic ~ 0.22 ~ ~ ~ 0.15 1.45 16.20 14.10 16.20 14.10 0.20 0.
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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 9 Revision History Table 9.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION Rev. 1.4 (06-20-08) Table 2.5, “System and Power Signals,” on page 17 Added text to VDD_CORE and VDD_PLL pin descriptions that states the pins must not be used to supply power to external devices. Figure 1.2 on page 11 Diagrams redone.