Datasheet
Table Of Contents
- Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 Transceiver
- 3.2 Auto-negotiation
- 3.3 HP Auto-MDIX Support
- 3.4 MAC Interface
- 3.5 Serial Management Interface (SMI)
- 3.6 Interrupt Management
- 3.7 Configuration Straps
- 3.8 Miscellaneous Functions
- 3.9 Application Diagrams
- 4.0 Register Descriptions
- 4.1 Register Nomenclature
- 4.2 Control and Status Registers
- TABLE 4-2: SMI Register Map
- 4.2.1 Basic Control Register
- 4.2.2 Basic Status Register
- 4.2.3 PHY Identifier 1 Register
- 4.2.4 PHY Identifier 2 Register
- 4.2.5 Auto Negotiation Advertisement Register
- 4.2.6 Auto Negotiation Link Partner Ability Register
- 4.2.7 Auto Negotiation Expansion Register
- 4.2.8 Mode Control/Status Register
- 4.2.9 Special Modes Register
- 4.2.10 Symbol Error Counter Register
- 4.2.11 Special Control/Status Indications Register
- 4.2.12 Interrupt Source Flag Register
- 4.2.13 Interrupt Mask Register
- 4.2.14 PHY Special Control/Status Register
- 5.0 Operational Characteristics
- 6.0 Package Information
- 7.0 Application Notes
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
LAN8720A/LAN8720AI
DS00002165B-page 10 2016 Microchip Technology Inc.
1 Ethernet TX/
RX Positive
Channel 2
RXP AIO Transmit/Receive Positive Channel 2
1 Ethernet TX/
RX Negative
Channel 2
RXN AIO Transmit/Receive Negative Channel 2
TABLE 2-5: MISCELLANEOUS PINS
Num PINs NAME SYMBOL
BUFFER
TYPE
DESCRIPTION
1 External
Cryst
al
Input
XTAL1 ICLK External crystal input
External
Clock Input
CLKIN ICLK Single-ended clock oscillator input.
Note: W
hen using a single ended clock
oscillator, XTAL2 should be left
unconnected.
1 External
Crystal Out-
put
XTAL2 OCLK External crystal output
1 External
Re
set
nRST VIS
(PU)
System reset. This signal is active low.
1 Interrupt Out-
put
nINT VOD8
(PU)
Active low interrupt output. Place an external
re
sistor pull-up to VDDIO.
Note: Refer to Section 3.6, "Interrupt
Management," on page 24 for additional
details on device interrupts.
Note: Refer to Section 3.8.1.2, "nINTSEL and
LED2 Polarity Selection," on page 32 for
details on how the nINTSEL configuration
strap is used to determine the function of
this pin.
Reference
Clock Output
REFCLKO VO8 This optional 50MHz clock output is derived from
the 25MHz crystal oscillator. REFCLKO is select-
able via the nINTSEL configuration strap.
Note: Refer Section 3.7.4.2, "REF_CLK Out
Mode," on page 29 for additional details.
Note: Re
fer to Section 3.8.1.2, "nINTSEL and
LED2 Polarity Selection," on page 32 for
details on how the
nINTSEL configuration
strap is used to determine the function of
this pin.
TABLE 2-4: ETHERNET PINS (CONTINUED)
Num PINs NAME SYMBOL
BUFFER
TYPE
DESCRIPTION