Datasheet

LAN8720A/LAN8720AI
DS00002165B-page 62  2016 Microchip Technology Inc.
5.5.4.3 RMII CLKIN Requirements
TABLE 5-11: RMII CLKIN (REF_CLK) TIMING VALUES
Parameter Min Typ Max Units Notes
CLKIN frequency 50 — MHz —
CLKIN Frequency Drift — ± 50 ppm —
CLKIN Duty Cycle 40 — 60 % —
CLKIN Jitter — 150 psec p-p – not RMS
5.5.5 SMI TIMING
This section specifies the SMI timing of the device. Please refer to Section 3.5, Serial Management Interface (SMI) for
additional details.
FIGURE 5-6: SMI TIMING
MDC
MDIO
t
clkh
t
clkl
t
clkp
t
ohold
MDIO
t
su
t
ihold
(Data-Out)
(Data-In)
t
ohold
t
val
TABLE 5-12: SMI TIMING VALUES
Symbol Description Min Max Units Notes
t
clkp
MDC period 400 — ns —
t
clkh
MDC high time 160 (80%) — ns —
t
clkl
MDC low time 160 (80%) — ns —
t
val
MDIO (read from PHY) output valid from rising
edge of MDC
— 300 ns —
t
ohold
MDIO (read from PHY) output hold from rising
edge of MDC
0 — ns —
t
su
MDIO (write to PHY) setup time to rising edge of
MDC
10 — ns —
t
ihold
MDIO (write to PHY) input hold time after rising
edge of MDC
10 — ns —