Datasheet

LAN8720A/LAN8720AI
DS00002165B-page 60  2016 Microchip Technology Inc.
5.5.4 RMII INTERFACE TIMING
5.5.4.1 RMII Timing (REF_CLK Out Mode)
The 50MHz REF_CLK OUT timing applies to the case when nINTSEL is pulled-low. In this mode, a 25MHz crystal or
clock oscillator must be input on the XTAL1/CLKIN and XTAL2 pins. For more information on REF_CLK Out Mode, see
Section 3.7.4.2, REF_CLK Out Mode.
FIGURE 5-4: RMII TIMING (REF_CLK OUT MODE)
REFCLKO
RXD[1:0],
RXER
CRS_DV
t
clkh
t
clkl
t
clkp
t
oval
t
ohold
t
oval
t
oval
t
ohold
t
su
TXD[1:0]
TXEN
t
ihold
t
su
t
ihold
t
ihold
t
su
t
ihold
TABLE 5-9: RMII TIMING VALUES (REF_CLK OUT MODE)
Symbol Description Min Max Units Notes
t
clkp
REFCLKO period 20 — ns —
t
clkh
REFCLKO high time t
clkp
*0.4 t
clkp
*0.6 ns —
t
clkl
REFCLKO low time t
clkp
*0.4 t
clkp
*0.6 ns —
t
oval
RXD[1:0], RXER, CRS_DV output valid from ris-
ing edge of REFCLKO
— 5.0 ns Note 5-24
t
ohold
RXD[1:0], RXER, CRS_DV output hold from ris-
ing edge of REFCLKO
1.4 — ns Note 5-24
t
su
TXD[1:0], TXEN setup time to rising edge of
REFCLKO
7.0 — ns Note 5-24
t
ihold
TXD[1:0], TXEN input hold time after rising edge
of REFCLKO
2.0 — ns Note 5-24
Note 5-24 T
iming was designed for system load between 10 pf and 25 pf.