Datasheet

LAN8720A/LAN8720AI
DS00002165B-page 58  2016 Microchip Technology Inc.
5.5.2 POWER SEQUENCE TIMING
This diagram illustrates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and magnetics power
supplies can turn on in any order provided they all reach operational levels within the specified time period t
pon
. Device
power supplies can turn off in any order provided they all reach 0 volts within the specified time period p
off
.
FIGURE 5-2: POWER SEQUENCE TIMING
VDDIO
Magnetics
Power
t
pon
t
poff
VDD1A,
VDD2A
TABLE 5-7: POWER SEQUENCE TIMING VALUES
Symbol Description Min Typ Max Units
t
pon
Power supply turn on time — — 50 mS
t
poff
Power supply turn off time — — 500 mS
Note: Wh
en the internal regulator is disabled, a power-up sequencing relationship exists between VDDCR and
the 3.3V power supply. For additional information refer to Section 3.7.4, REGOFF: Internal +1.2V Regula-
tor Configuration.
5.5.3 POWER-ON NRST & CONFIGURATION STRAP TIMING
This diagram illustrates the nRST reset and configuration strap timing requirements in relation to power-on. A hardware
reset (nRST assertion) is required following power-up. For proper operation, nRST must be asserted for no less than
t
rstia
. The nRST pin can be asserted at any time, but must not be deasserted before t
purstd
after all external power sup-
plies have reached 80% of their nominal operating levels. In o
rder for valid configuration strap values to be read at
power-up, the t
css
and t
csh
timing constraints must be followed. Refer to Section 3.8.5, Resets for additional information.