Datasheet
Table Of Contents
- Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 Transceiver
- 3.2 Auto-negotiation
- 3.3 HP Auto-MDIX Support
- 3.4 MAC Interface
- 3.5 Serial Management Interface (SMI)
- 3.6 Interrupt Management
- 3.7 Configuration Straps
- 3.8 Miscellaneous Functions
- 3.9 Application Diagrams
- 4.0 Register Descriptions
- 4.1 Register Nomenclature
- 4.2 Control and Status Registers
- TABLE 4-2: SMI Register Map
- 4.2.1 Basic Control Register
- 4.2.2 Basic Status Register
- 4.2.3 PHY Identifier 1 Register
- 4.2.4 PHY Identifier 2 Register
- 4.2.5 Auto Negotiation Advertisement Register
- 4.2.6 Auto Negotiation Link Partner Ability Register
- 4.2.7 Auto Negotiation Expansion Register
- 4.2.8 Mode Control/Status Register
- 4.2.9 Special Modes Register
- 4.2.10 Symbol Error Counter Register
- 4.2.11 Special Control/Status Indications Register
- 4.2.12 Interrupt Source Flag Register
- 4.2.13 Interrupt Mask Register
- 4.2.14 PHY Special Control/Status Register
- 5.0 Operational Characteristics
- 6.0 Package Information
- 7.0 Application Notes
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service

TABLE 5-4: VARIABLE I/O BUFFER CHARACTERISTICS
Parameter Symbol Min
1.8V
Typ
2.5V
Ty
p
3.3V
Typ
Max Units Notes
VIS Type Input Buffer
Low Input Level
High Input Level
Neg-Going Threshold
Pos-Going Threshold
Schmitt Trigger Hyster-
esis (V
IHT
- V
ILT
)
Input Leakage
(V
IN
= VSS or VDDIO)
Input Capacitance
V
ILI
V
IHI
V
ILT
V
IHT
V
HYS
I
IH
C
IN
-0.3
0.64
0.81
102
-10
0.83
0.99
158
1.15
1.29
136
1.41
1.65
138
3.6
1.76
1.90
288
10
2
V
V
V
V
mV
uA
pF
Schmitt trigger
Schmitt trigger
Note 5-11
VO8 Type Buffers
Low Output Level
High Output Level
V
OL
V
OH
VDDIO -
0.4
0.4 V
V
I
OL
= 8mA
I
OH
= -8mA
VOD8 Type Buffer
Low Output Level V
OL
0.4 V I
OL
= 8mA
LAN8720A/LAN8720AI
DS00002165B-page 56 2016 Microchip Technology Inc.
Note 5-14 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up
resistors add +/- 50uA per-pin (typical).
TABLE 5-5: 100BASE-TX TRANSCEIVER CHARACTERISTICS
Parameter Symbol Min Typ Max Units Notes
Peak Differential Output Voltage High V
PPH
950 — 1050 mVpk Note 5-12
Peak Differential Output Voltage Low V
PPL
-950 — -1050 mVpk Note 5-12
Signal Amplitude Symmetry V
SS
98 — 102 % Note 5-12
Signal Rise and Fall Time T
RF
3.0 — 5.0 nS Note 5-12
Rise and Fall Symmetry T
RFS
— — 0.5 nS Note 5-12
Duty Cycle Distortion D
CD
35 50 65 % Note 5-13
Overshoot and Undershoot V
OS
— — 5 % —
Jitter — — — 1.4 nS Note 5-14
Note 5-15 Measu
red at line side of transformer, line replaced by 100 (+/- 1%) resistor.
Note 5-16 Of
fset from 16nS pulse width at 50% of pulse peak.