Datasheet
Table Of Contents
- Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 Transceiver
- 3.2 Auto-negotiation
- 3.3 HP Auto-MDIX Support
- 3.4 MAC Interface
- 3.5 Serial Management Interface (SMI)
- 3.6 Interrupt Management
- 3.7 Configuration Straps
- 3.8 Miscellaneous Functions
- 3.9 Application Diagrams
- 4.0 Register Descriptions
- 4.1 Register Nomenclature
- 4.2 Control and Status Registers
- TABLE 4-2: SMI Register Map
- 4.2.1 Basic Control Register
- 4.2.2 Basic Status Register
- 4.2.3 PHY Identifier 1 Register
- 4.2.4 PHY Identifier 2 Register
- 4.2.5 Auto Negotiation Advertisement Register
- 4.2.6 Auto Negotiation Link Partner Ability Register
- 4.2.7 Auto Negotiation Expansion Register
- 4.2.8 Mode Control/Status Register
- 4.2.9 Special Modes Register
- 4.2.10 Symbol Error Counter Register
- 4.2.11 Special Control/Status Indications Register
- 4.2.12 Interrupt Source Flag Register
- 4.2.13 Interrupt Mask Register
- 4.2.14 PHY Special Control/Status Register
- 5.0 Operational Characteristics
- 6.0 Package Information
- 7.0 Application Notes
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service

2016 Microchip Technology Inc. DS00002165B-page 55
LAN8720A/LAN8720AI
5.4 DC Specifications
TABLE 5-2: details the non-variable I/O buffer characteristics. These buffer types do not support variable voltage oper-
ation. TABLE 5-3: details the variable voltage I/O buffer characteristics. Typical values are provided for 1.8V, 2.5V, and
3.3V VDDIO cases.
TABLE 5-3: NON-VARIABLE I/O BUFFER CHARACTERISTICS
Parameter Symbol Min Typ Max Units Notes
IS Type Input Buffer
Low Input Level
High Input Level
Negative-Going Threshold
Positive-Going Threshold
Schmitt Trigger Hysteresis
(V
IHT
- V
ILT
)
Input Leakage
(V
IN
= VSS or VDDIO)
Input Capacitance
V
ILI
V
IHI
V
ILT
V
IHT
V
HYS
I
IH
C
IN
-0.3
1.01
1.39
336
-10
1.19
1.59
399
3.6
1.39
1.79
459
10
2
V
V
V
V
mV
uA
pF
Schmitt trigger
Schmitt trigger
Note 5-9
O12 Type Buffers
Low Output Level
High Output Level
V
OL
V
OH
VDD2A -
0.4
0.4 V
V
I
OL
= 12mA
I
OH
= -12mA
ICLK Type Buffer
(XT
AL1 Input)
Low Input Level
High Input Level
V
ILI
V
IHI
-0.3
0.9
0.35
3.6
V
V
Note 5-10
Note 5-12 This specification applies
to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up
resistors add +/- 50uA per-pin (typical).
Note 5-13 XT
AL1/CLKIN can optionally be driven from a 25MHz single-ended clock oscillator.