Datasheet
Table Of Contents
- Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 Transceiver
- 3.2 Auto-negotiation
- 3.3 HP Auto-MDIX Support
- 3.4 MAC Interface
- 3.5 Serial Management Interface (SMI)
- 3.6 Interrupt Management
- 3.7 Configuration Straps
- 3.8 Miscellaneous Functions
- 3.9 Application Diagrams
- 4.0 Register Descriptions
- 4.1 Register Nomenclature
- 4.2 Control and Status Registers
- TABLE 4-2: SMI Register Map
- 4.2.1 Basic Control Register
- 4.2.2 Basic Status Register
- 4.2.3 PHY Identifier 1 Register
- 4.2.4 PHY Identifier 2 Register
- 4.2.5 Auto Negotiation Advertisement Register
- 4.2.6 Auto Negotiation Link Partner Ability Register
- 4.2.7 Auto Negotiation Expansion Register
- 4.2.8 Mode Control/Status Register
- 4.2.9 Special Modes Register
- 4.2.10 Symbol Error Counter Register
- 4.2.11 Special Control/Status Indications Register
- 4.2.12 Interrupt Source Flag Register
- 4.2.13 Interrupt Mask Register
- 4.2.14 PHY Special Control/Status Register
- 5.0 Operational Characteristics
- 6.0 Package Information
- 7.0 Application Notes
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service

LAN8720A/LAN8720AI
DS00002165B-page 48 2016 Microchip Technology Inc.
4.2.9 SPECIAL MODES REGISTER
Index (In Decimal): 18 Size: 16 bits
Bits Description Type Default
15 RESERVED RO —
14 RESERVED
Write as 1, ignore on read.
R/W
NASR
1b
13:8 RESERVED RO —
7:5 MODE
Transceiver mode of operation. Refer to Section 3.7.2, MODE[2:0]: Mode
Configuration for additional details.
R/W
NASR
Note 4-5
4:0 PHYAD
PHY Address. The PHY Address is used for the SMI address and for initial-
ization of the Cipher (Scrambler) key. Refer to Section 3.7.1, PHYAD[2:0]:
PHY Address Configuration for additional details.
R/W
NASR
Note 4-6
Note 4-4 The de
fault value of this field is determined by the MODE[2:0] configuration straps. Refer to
Section 3.7.2, MODE[2:0]: Mode Configuration for additional information.
Note 4-5 The de
fault value of this field is determined by the PHYAD[0] configuration strap. Refer to
Section 3.7.1, PHYAD[2:0]: PHY Address Configuration for additional information.
4.2.10 SYMBOL ERROR COUNTER REGISTER
Index (In Decimal): 26 Size: 16 bits
8:7 RESERVED RO —
6 ALTINT
Alternate Interrupt Mode:
0 = Primary interrupt system enabled (Default)
1 = Alternate interrupt system enabled
Refer to Section 3.6, Interrupt Management for additional information.
R/W 0b
5:2 RESERVED RO —
1 ENERGYON
Indicates whether energy is detected. This bit transitions to “0” if no valid
e
nergy is detected within 256ms. It is reset to “1” by a hardware reset and is
unaffected by a software reset. Refer to Section 3.8.3.2, Energy Detect
Power-Down for additional information.
RO 1b
0 RESERVED R/W 0b
Bits Description Type Default