Datasheet

LAN8720A/LAN8720AI
DS00002165B-page 34  2016 Microchip Technology Inc.
3.8.6 CARRIER SENSE
The carrier sense (CRS) is output on the CRS_DV pin. CRS is a signal defined by the MII specification in the IEEE
802.3u standard. The device asserts CRS based only on receive activity whenever the transceiver is either in repeater
mode or full-duplex mode. Otherwise the transceiver asserts CRS based on either transmit or receive activity.
The carrier sense logic uses the encoded, unscrambled data to de
termine carrier activity status. It activates carrier
sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 con-
secutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is
asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after
the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE
followed by some non-IDLE symbol.
3.8.7 LINK INTEGRITY TEST
The device performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram.
The link status is multiplexed with the 10Mbps link status to form the Link Status bit in the Basic Status Register and to
drive the LINK LED (LED1).
The DSP indicates a valid MLT-3 waveform present on the RXP a
nd RXN signals as defined by the ANSI X3.263 TP-
PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is
asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When
received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negoti-
ation be disabled, the link integrity logic moves immediately to
the Link-Up state when the DATA_VALID is asserted.
To allow the line to stabilize, the link integrity logic will wait a minimum of 330 sec fr
om the time DATA_VALID is
asserted until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will
immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10BASE-
T mode, the link status is derived from the 10BASE-T receiver logic.
3.8.8 LOOPBACK OPERATION
The device may be configured for near-end loopback and far loopback. These loopback modes are detailed in the fol-
lowing subsections.
3.8.8.1 Near-end Loopback
Near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indi-
cated by the blue arrows in Figure 3-9. The near-end loopback mode is enabled by setting the Loopback bit of the Basic
Control Register to “1”. A large percentage of the digital circuitry is o
perational in near-end loopback mode because data
is routed through the PCS and PMA layers into the PMD sublayer before it is looped back. The transmitters are powered
down regardless of the state of TXEN.
FIGURE 3-12: NEAR-END LOOPBACK BLOCK DIAGRAM
SMSC
Ethernet Transceiver
10/100
Ethernet
MAC
CAT-5
XFMR
Digital
RXD
TXD
Analog
RX
TX
X
X