Datasheet

 2016 Microchip Technology Inc. DS00002165B-page 33
LAN8720A/LAN8720AI
3.8.2 VARIABLE VOLTAGE I/O
The device’s digital I/O pins are variable voltage, allowing them to take advantage of low power savings from shrinking
technologies. These pins can operate from a low I/O voltage of +1.62V up to +3.6V. The applied I/O voltage must main
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tain its value with a tolerance of ± 10%. Varying the voltage up or down after the transceiver has completed power-on
reset can cause errors in the transceiver operation. Refer to Section 5.0, "Operational Characteristics," on page 54 for
additional information.
Note: Input signals must not be driven high before power is applied to the device.
3.8.3 POWER-DOWN MODES
There are two device power-down modes: General Power-Down Mode and Energy Detect Power-Down Mode. These
modes are described in the following subsections.
3.8.3.1 General Power-Down
This power-down mode is controlled via the Power Down bit of the Basic Control Register. In this mode, the entire trans-
ceiver (except the management interface) is powered-down and remains in this mode as long as the Power Down bit is
“1”. When the Power Down bit is cleared, the transceiver powers up and is automatically reset.
3.8.3.2 Energy Detect Power-Down
This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status Register. In this mode,
when no energy is present on the line the transceiver is powered down (except for the management interface, the
SQUELCH circuit, and the ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy
from 100BASE-TX, 10BASE-T, or Auto-negotiation signals.
In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is powered-down
and nothing is transmitted. When energy is received via link pulses or packets, the ENERGYON bit goes high and the
transceiver powers-up. The device automatically resets into the state prior to power-down and asserts the nINT interrupt
if the ENERGYON interrupt is enabled in the Interrupt Mask Register. The first and possibly the second packet to acti-
vate ENERGYON may be lost.
When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is disabled.
3.8.4 ISOLATE MODE
The device data paths may be electrically isolated from the RMII interface by setting the Isolate bit of the Basic Control
Register to “1”. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does
respond to management transactions.
Isolation provides a means for multiple transceivers to be connected to the same RMII interface without contention. By
default, the transceiver is not isolated (on power-up (Isolate=0).
3.8.5 RESETS
The device provides two forms of reset: Hardware and Software. The device registers are reset by both Hardware and
Software resets. Select register bits, indicated as “NASR” in the register definitions, are not cleared by a Software reset.
The registers are not reset by the power-down modes described in
Section 3.8.3.
Note: For the first 16us after coming out of reset, the RMII interface will run at 2.5 MHz. After this time, it will switch
to 25 MHz if auto-negotiation is enabled.
3.8.5.1 Hardware Reset
A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum
time detailed in
Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page 59 to ensure a proper trans-
ceiver reset. During a Hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal.
Note: A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.5.3, "Power-On nRST
& Configuration Strap Timing," on page 59 for additional information.
3.8.5.2 Software Reset
A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All registers bits, except
those indicated as “NASR” in the register definitions, are cleared by a Software reset. The Soft Reset bit is self-clearing.
Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset process will be completed within 0.5s from the setting
of this bit.