Datasheet

LAN8720A/LAN8720AI
DS00002165B-page 28  2016 Microchip Technology Inc.
3.7.3 REGOFF: INTERNAL +1.2V REGULATOR CONFIGURATION
The incorporation of flexPWR technology provides the ability to disable the internal +1.2V regulator. When the regulator
is disabled, an external +1.2V must be supplied to the VDDCR pin. Disabling the internal +1.2V regulator makes it pos-
sible to reduce total system power, since an exter
nal switching regulator with greater efficiency (versus the internal linear
regulator) can be used to provide +1.2V to the transceiver circuitry.
Note: Because
the REGOFF configuration strap shares functionality with the LED1 pin, proper consideration must
also be given to the LED polarity. Refer to Section 3.8.1.1, "REGOF
F and LED1 Polarity Selection," on
page 33 for additional information on the relation between REGOFF and the LED1 polarity.
3.7.3.1 Disabling the Internal +1.2V Regulator
To disable the +1.2V internal regulator, a pull-up strapping resistor should be connected from the REGOFF configuration
strap to VDD2A. At power-on, after both VDDIO and VDD2A are within specification, the transceiver will sample
REGOFF to determine whether the internal regulator should turn on. If the pin is sampled at a voltage greater than V
IH
,
then the internal regulator is disabled and the system must supply +1.2V to the VDDCR pin. The VDDIO voltage must
be at least 80% of the operating voltage level (1.44V when operating at 1.8V, 2.0V when operating at 2.5V, 2.64V when
operating at 3.3V) before voltage is applied to VDDCR. As described in Section 3.7.4.2, when
REGOFF is left floating
or connected to VSS, the internal regulator is enabled and the system is not required to supply +1.2V to the VDDCR pin.
3.7.3.2 Enabling the Internal +1.2V Regulator
The +1.2V for VDDCR is supplied by the on-chip regulator unless the transceiver is configured for the regulator off mode
using the REGOFF configuration strap as described in Section 3.7.4.1. By default, the internal +1.2V regulator is
enabled when
REGOFF is floating (due to the internal pull-down resistor). During power-on, if REGOFF is sampled
below V
IL
, then the internal +1.2V regulator will turn on and operate with power from the VDD2A pin.
3.7.4 NINTSEL: NINT/REFCLKO CONFIGURATION
The nINTSEL configuration strap is used to select between one of two available modes: REF_CLK In Mode (nINT) and
REF_CLK Out Mode. The configured mode determines the function of the nINT/REFCLKO pin. The nINTSEL configu-
ration strap is latched at POR
and on the rising edge of the nRST. By default, nINTSEL is configured for nINT mode via
the internal pull-up resistor.
TABLE 3-6: NINTSEL CONFIGURATION
Strap Value Mode REF_CLK description
nINTSEL = 0 REF_CLK Out Mode nINT/REFCLKO is the source of REF_CLK.
nINTSEL = 1 REF_CLK In Mode nINT/REFCLKO is an active low interrupt output. 
The REF_CLK is sourced externally and must be driven
on the XTAL1/CLKIN pin.
The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0]
and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path.
However, on the receive data path, the receiver recovers the clock from the incoming data stream. The device uses
elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK.
In REF_CLK In Mode, the 50MHz REF_CLK is driven on the XT
AL1/CLKIN pin. This is the traditional system configu-
ration when using RMII, and is described in Section 3.7.4.1. When configured for REF_CLK Out Mode, the device gen-
erates the 50MHz RMII REF_CLK and the nINT interrupt is not available. REF_CLK Out Mode allows a low-cost 25MHz
crystal to be used as the reference for REF_CLK. This configuration may result in reduced system cost and is described
in Section 3.7.4.2.
MODE[2] CRS_DV/
MODE2
TABLE 3-5: PIN NAMES FOR MODE BITS
MODE Bit Pin Name