Datasheet
Table Of Contents
- Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
- 1.0 Introduction
- 2.0 Pin Description and Configuration
- 3.0 Functional Description
- 3.1 Transceiver
- 3.2 Auto-negotiation
- 3.3 HP Auto-MDIX Support
- 3.4 MAC Interface
- 3.5 Serial Management Interface (SMI)
- 3.6 Interrupt Management
- 3.7 Configuration Straps
- 3.8 Miscellaneous Functions
- 3.9 Application Diagrams
- 4.0 Register Descriptions
- 4.1 Register Nomenclature
- 4.2 Control and Status Registers
- TABLE 4-2: SMI Register Map
- 4.2.1 Basic Control Register
- 4.2.2 Basic Status Register
- 4.2.3 PHY Identifier 1 Register
- 4.2.4 PHY Identifier 2 Register
- 4.2.5 Auto Negotiation Advertisement Register
- 4.2.6 Auto Negotiation Link Partner Ability Register
- 4.2.7 Auto Negotiation Expansion Register
- 4.2.8 Mode Control/Status Register
- 4.2.9 Special Modes Register
- 4.2.10 Symbol Error Counter Register
- 4.2.11 Special Control/Status Indications Register
- 4.2.12 Interrupt Source Flag Register
- 4.2.13 Interrupt Mask Register
- 4.2.14 PHY Special Control/Status Register
- 5.0 Operational Characteristics
- 6.0 Package Information
- 7.0 Application Notes
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Product Identification System
- Worldwide Sales and Service
2016 Microchip Technology Inc. DS00002165B-page 27
LAN8720A/LAN8720AI
The device’s SMI address may be configured using hardware configuration to either the value 0 or 1. The user can con-
figure the PHY address using Software Configuration if an address greater than 1 is required. The PHY address can be
written (after SMI communication at some address is established) using the PHYAD bits of the Special Modes Register.
The
PHYAD0 hardware configuration strap is multiplexed with the RXER pin.
3.7.2 MODE[2:0]: MODE CONFIGURATION
The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the nRST pin is deas-
serted, the register bit values are loaded according to the MODE[2:0] configuration straps. The 10/100 digital block is
then configured by the register bit values. When a soft reset occurs via the Soft Reset bit of the Basic Control Register,
the configuration of the 10/100 digit
al block is controlled by the register bit values and the MODE[2:0] configuration
straps have no affect.
The device’s mode may be configured using the hardware configuration straps as summarized in Table 3-6. The user
may configure the transceiver mode
by writing the SMI registers.
TABLE 3-4: MODE[2:0] BUS
MODE[2:0] Mode Definitions
Default Register Bit Values
Register 0 Register 4
[13,12,10,8] [8,7,6,5]
000 10Base-T Half Duplex. Auto-negotiation disabled. 0000 N/A
001 10Base-T Full Duplex. Auto-negotiation disabled. 0001 N/A
010 100Base-TX Half Duplex. Auto-negotiation dis-
abled.
CRS is active during Transmit & Receive.
1000 N/A
011 100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
1001 N/A
100 100Base-TX Half Duplex is advertised. Auto-negoti-
ation enabled.
CRS is active during Transmit & Receive.
1100 0100
101 Repeater mode. Auto-negotiation enabled.
100
Base-TX Half Duplex is advertised.
CRS is active during Receive.
1100 0100
110 Power Down mode. In this mode the transceiver will
wake
-up in Power-Down mode. The transceiver
cannot be used when the MODE[2:0] bits are set to
this mode. To exit this mode, the MODE bits in Reg-
ister 18.7:5(see Section 4.2.9, "Special Modes Reg-
ister," on page 50) must be configured to some
other value and a soft reset must be issued.
N/A N/A
111 All capable. Auto-negotiation enabled. X10X 1111
The MODE[2:0] hardware configuration pins are multipl
exed with other signals as shown in Table 3-5.
TABLE 3-5: PIN NAMES FOR MODE BITS
MODE Bit Pin Name
MODE[0] RXD0/
MODE0
MODE[1] RXD1/MODE1