Datasheet

LAN8720A/LAN8720AI
DS00002165B-page 24  2016 Microchip Technology Inc.
FIGURE 3-6:
MDC
MDIO
...
32 1's 0 1 10 A4A3A2A1A0R4R3R2R1R0
Write Cycle
D15 D14 D1 D0
...
DataPreamble
Start of
Frame
OP
Code
PHY Address Register Address
Turn
Around
Data To Phy
MDIO TIMING AND FRAME STRUCTURE - WRITE CYCLE
3.6 Interrupt Management
The device management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. This
interrupt capability generates an active low asynchronous interrupt signal on the nINT output whenever certain events
are detected as setup by the Interrupt Mask Register.
The device’s interrupt system provides two
modes, a Primary Interrupt mode and an Alternative interrupt mode. Both
systems will assert the nINT pin low when the corresponding mask bit is set. These modes differ only in how they de-
assert the nINT interrupt output. These modes are detailed in the following subsections.
Note: Th
e Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative
interrupt mode requires setup after a power-up or hard reset.
3.6.1 PRIMARY INTERRUPT SYSTEM
The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is “0”). The
Primary interrupt system is always selected after power-up or hard reset. In this mode, to set an interrupt, set the cor-
responding mask bit in the Interrupt Mask Register (see Table 3-3). Then when the event to assert nINT is true, the nINT
output will be asserted. When the corresponding event to deassert nINT is tru
e, then the nINT will be de-asserted.
TABLE 3-2: INTERRUPT MANAGEMENT TABLE
Mask Interrupt Source Flag Interrupt Source
Event to Assert
nI
NT
Event to
De-Assert nINT
30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1
(Note 3-3)
Falling 17.1 or
Reading register 29
30.6 29.6 Auto-Negotiation
complete
1.5 Auto-Negotiate
Comple
te
Rising 1.5 Falling 1.5 or
Reading register 29