Datasheet

LAN8720A/LAN8720AI
DS00002165B-page 18  2016 Microchip Technology Inc.
Special logic in the descrambler ensures synchronization with the remote transceiver by searching for IDLE symbols
within a window of 4000 bytes (40us). This window ensures that a maximum packet size of 1514 bytes, allowed by the
IEEE 802.3 standard, can be received with no interference. If no IDLE-symbols are detected within this time-period,
receive operation is aborted and the descrambler re-starts the synchronization process.
3.1.2.5 Alignment
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD)
pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of
frame.
3.1.2.6 5B/4B Decoding
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The translated data is pre-
sented on the RXD[1:0] signal lines. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC pre-
amble. Reception of the SSD causes the transceiver to assert the receive data valid signal, indicating that valid data is
available on the RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End of
Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assert
the carrier sense and receive data valid signals.
Note: Th
ese symbols are not translated into data.
3.1.2.7 Receive Data Valid Signal
The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the
RXD[1:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXD
is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure
or SIGDET becomes false.
RXDV is asserted when the first nibble of tra
nslated /J/K/ is ready for transfer over the Media Independent Interface (MII
mode).
FIGURE 3-3:
5D5 data data data data
RXD
RX_DV
RX_CLK
5D5
data data data data
CLEAR-TEXT
5JK
5 55
TR
Idle
RELATIONSHIP BETWEEN RECEIVED DATA AND SPECIFIC MII SIGNALS
3.1.2.8 Receiver Errors
During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0
through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER signal is asserted and arbitrary
data is driven onto the RXD[1:0] lines. Should an error be detected during the time that the /J/K/ delimiter is being
decoded (bad SSD error), RXER is asserted true and the value ‘1110’ is driven onto the RXD[1:0] lines. Note that the
Valid Data signal is not yet asserted when the bad SSD error occurs.
3.1.2.9 100M Receive Data Across the RMII Interface
The 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate of 50MHz.
The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK). To ensure that the setup and hold
requirements are met, the nibbles are clocked out of the transceiver on the falling edge of XTAL1/CLKIN (REF_CLK).
3.1.3 10BASE-T TRANSMIT
Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit nibbles from the
MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester-encoded
and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.
The 10M transmitter uses the following blocks: