Datasheet

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
®
Technology in a Small Footprint
Datasheet
SMSC LAN8700/LAN8700i 75 Revision 2.3 (04-12-11)
DATASHEET
Chapter 8 Application Notes
8.1 Application Diagram
Note: R5 on the Crystal is used to control the crystal drive strength into the PHY clock generator.
This resistance can be fine tuned to meet the requirements of each crystal manufacturer.
Figure 8.1 Simplified Application Diagram (see Section 8.4, "Reference Designs")
Host System
MAC
(Media Access Controller)
MII/RMII
RX_CLK/REGOFF
nINT/TX_ER/TXD4
MDC
CRS/PHYAD4
MDIO
nRST
TX_EN
VDD_CORE
VDD33
LINK/PHYAD1
ACTIVITY/PHYAD2
FDUPLEX/PHYAD3
XTAL2
CLKIN/XTAL1
RXD3/nINTSEL
RXD1/MODE1 RXD2/MODE2
TXD3
TX_CLK
RX_ER/RXD4
VDDIO
TXD1
TXD0
TXD2
COL/RMII/CRS_DV
TXP
RXN
EXRES1
VDDA3.3 RXP
VDDA3.3
1
2
3
4
5
6
7
8
LAN8700/LAN8700I
MII/RMII Ethernet PHY
36 Pin QFN
GND FLAG
10 11 12 13
14 15 16
24
23
22
21
20
19
32 31 30 29 28
SPEED100/PHYAD0
9
RX_DV
RXD0/MODE0
17
TXN
18
27
26
25
36 35 34 33
VDDIO
4.7uF
0.1uF
Variable
Voltage
IO Regulator
Integrated
Magnetics and RJ45 Jack
12.4k 1%
4.7uF
0.1uF
R1
R2
VDD3.3
4.7uF
0.1uF
VDD3.3
Voltage
Regulator
0.1uF
Speed100
Link
Activity
FullDuplex
R3
R4
VDDA3.3
0.1uF
0.1uF
0.1uF
1
2
3
4
5
6
7
8