Datasheet

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
®
Technology in a Small Footprint
Datasheet
Revision 2.3 (04-12-11) 28 SMSC LAN8700/LAN8700i
DATASHEET
is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal
decoding takes place.
4.6.3 MII vs. RMII Configuration
The LAN8700/LAN8700i must be configured to support the MII or RMII bus for connectivity to the MAC.
This configuration is done through the COL/RMII/CRS_DV pin. To select MII mode, float the
COL/RMII/CRS_DV pin. To select RMII mode, pull the pin high with an external resistor (see Ta ble 4.3,
“Boot Strapping Configuration Resistors,” on page 33) to VDDIO. On the rising edge of the internal
reset (nreset), the register bit 18.14 (MIIMODE) is loaded based on the strapping of the
COL/RMII/CRS_DV pin.
Most of the MII and RMII pins are multiplexed. Table 4.2, "MII/RMII Signal Mapping", shown below,
describes the relationship of the related device pins to what pins are used in MII and RMII mode.
Note 4.1 In RMII mode, this pin needs to tied to VSS.
Note 4.2 The RX_ER signal is optional on the RMII bus. This signal is required by the PHY, but it
is optional for the MAC. The MAC can choose to ignore or not use this signal.
Table 4.2 MII/RMII Signal Mapping
SIGNAL NAME MII MODE RMII MODE
TXD0 TXD0 TXD0
TXD1 TXD1 TXD1
TX_EN TX_EN TX_EN
RX_ER/
RXD4
RX_ER/
RXD4/
RX_ER
Note 4.2
COL/RMII/CRS_DV COL CRS_DV
RXD0 RXD0 RXD0
RXD1 RXD1 RXD1
TXD2 TXD2 Note 4.1
TXD3 TXD3 Note 4.1
TX_ER/
TXD4
TX_ER/
TXD4
CRS CRS
RX_DV RX_DV
RXD2 RXD2
RXD3/
nINTSEL
RXD3
TX_CLK TX_CLK
RX_CLK RX_CLK
CLKIN/XTAL1 CLKIN/XTAL1 REF_CLK