Datasheet

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
®
Technology in a Small Footprint
Datasheet
Revision 2.3 (04-12-11) 16 SMSC LAN8700/LAN8700i
DATASHEET
Note 3.1 On nRST transition high, the PHY latches the state of the configuration pins in this table.
RXD1/
MODE1
IOPU PHY Operating Mode Bit 1: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 56, for
the MODE options.
Note: This signal is mux’d with RXD1
RXD0/
MODE0
IOPU PHY Operating Mode Bit 0: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 56, for
the MODE options.
Note: This signal is mux’d with RXD0
COL/
RMII/
CRS_DV
IOPD Digital Communication Mode: set the digital communications
mode of the PHY to RMII or MII. This signal is muxed with the
Collision signal (MII mode) and Carrier Sense/ receive Data Valid
(RMII mode)
 Float for MII mode.
 Pull up with a resistor to VDDIO for RMII mode (see Table 4.3,
“Boot Strapping Configuration Resistors,” on page 33) .
RXD3/
nINTSEL
IOPU nINT pin mode select: set the mode of pin 1.
 Default, left floating pin 1 is nINT, active low interrupt output.
Notes:For nINT mode, tie nINT/TXD4/TXER to VDDIO with a
resistor (see Table 4.3, “Boot Strapping Configuration Resistors,”
on page 33).
 Pulled to VSS by a resistor, (see Table 4.3, “Boot Strapping
Configuration Resistors,” on page 33) pin 1 is TX_ER/TXD4,
Transmit Error or Transmit data 4 (5B mode).
Notes:For TXD4/TXER mode, do not tie nINT/TXD4/TXER to
VDDIO or Ground.
Table 3.5 General Signals
SIGNAL NAME TYPE DESCRIPTION
nINT/
TX_ER/
TXD4
IOPU LAN Interrupt – Active Low output. Place an external resistor
(see Table 4.3, “Boot Strapping Configuration Resistors,” on
page 33) pull-up to VCC 3.3V.
Notes:
 This signal is mux’d with TXER/TXD4
 See Section 4.10, "nINT/TX_ER/TXD4 Strapping," on page 32
for additional details on Strapping options.
nRST I External Reset – input of the system reset. This signal is active
LOW. When this pin is deasserted, the mode register bits are
loaded from the mode pins as described in Section 5.4.9.2.
Table 3.4 Boot Strap Configuration Inputs (Note 3.1) (continued)
SIGNAL NAME TYPE DESCRIPTION