Datasheet

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185 9 Revision 0.8 (06-12-08)
DATASHEET
Chapter 2 Pin Configuration
Figure 2.1 Package Pinout
LAN83C185
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TXD0
TXD1
TXD2
TXD3
TX_ER/TXD4
TX_EN
TX_CLK
RXD0 RXD1 RXD2 RXD3
RX_ER/RXD4
RX_DV
RX_CLK
CRS
COL
MDC
MDIO
TXP
TXN
RXP
RXN
S
PEED100/PHYAD0
LINKON/PHYAD1
ACTIVITY/PHYAD2
FDUPLEX/PHYAD3
GPO1/PHYAD4
MODE0
MODE1
MODE2
TEST0
TEST1
CLK_FREQ
REG_EN
GPO0/MII
GPO2 nINT
nRST
CLKIN/XTAL1
XTAL2
NC1
EXRES1
NC2
AVDD1 AVDD2 AVDD3 AVDD4
AVSS1 AVSS2 AVSS3
AVSS4 AVSS5
VREG
VDD_CORE
VDD1
VDD2
VDD3
VSS1
VSS3 VSS4 VSS5
VSS6
VSS7
VSS2