Datasheet

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Revision 0.8 (06-12-08) 58 SMSC LAN83C185
DATASHEET
12 REG_EN
1 MII -4 mA +8 mA +0.4 V VDD –
+0.4 V
Table 6.7 General Signals
PIN NO. NAME V
IH
V
IL
I
OH
I
OL
V
OL
V
OH
1 GPO0 -4 mA +8 mA +0.4 V VDD –
+0.4 V
2 GPO1 -4 mA +8 mA +0.4 V VDD –
+0.4 V
3 GPO2 -4 mA +8 mA +0.4 V VDD –
+0.4 V
46 nINT -4 mA +8 mA +0.4 V VDD –
+0.4 V
25 nRST
23 CLKIN/XTAL1
22 XTAL2
64 NC1
Table 6.8 Analog References
PIN NO. NAME V
IH
V
IL
I
OH
I
OL
V
OL
V
OH
59 EXRES1
56 NC2
Table 6.9 Internal Pull-Up / Pull-/Down Configurations
PIN NO. NAME PULL-UP OR PULL-DOWN TYPE
1 GPO0/MII Pull-down 30 uA
2 GPO1/PHYAD4 Pull-up 30 uA
4 MODE0 Pull-up 30 uA
5 MODE1 Pull-up 30 uA
6 MODE2 Pull-up 30 uA
9 TEST0 Pull-down 30 uA
10 TEST1 Pull-down 30 uA
Table 6.6 Configuration Inputs (continued)
PIN NO. NAME V
IH
V
IL
I
OH
I
OL
V
OL
V
OH