Datasheet

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Revision 0.8 (06-12-08) 56 SMSC LAN83C185
DATASHEET
6.5.3 DC Characteristics - Input and Output Buffers
Table 6.3 MII Bus Interface Signals
PIN NO. NAME V
IH
V
IL
I
OH
I
OL
V
OL
V
OH
41 TXD0 +2.0 V +0.8 V
42 TXD1 +2.0 V +0.8 V
44 TXD2 +2.0 V +0.8 V
45 TXD3 +2.0 V +0.8 V
37 TX_ER/TXD4 +2.0 V +0.8 V
39 TX_EN +2.0 V +0.8 V
38 TX_CLK -8 mA +8 mA +0.4 V VDD –
+0.4 V
32 RXD0 -8 mA +8 mA +0.4 V VDD –
+0.4 V
31 RXD1 -8 mA +8 mA +0.4 V VDD –
+0.4 V
30 RXD2 -8 mA +8 mA +0.4 V VDD –
+0.4 V
29 RXD3 -8 mA +8 mA +0.4 V VDD –
+0.4 V
35 RX_ER/RXD4 -8 mA +8 mA +0.4 V VDD –
+0.4 V
33 RX_DV -8 mA +8 mA +0.4 V VDD –
+0.4 V
34 RX_CLK -8 mA +8 mA +0.4 V VDD –
+0.4 V
48 CRS -8 mA +8 mA +0.4 V VDD –
+0.4 V
47 COL -8 mA +8 mA +0.4 V VDD –
+0.4 V
27 MDC +2.0 V +0.8 V
26 MDIO -8 mA +8 mA +0.4 V VDD –
+0.4 V