Datasheet

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185 33 Revision 0.8 (06-12-08)
DATASHEET
5.1 SMI Register Mapping
The following registers are supported (register numbers are in decimal):
5.2 SMI Register Format
The mode key is as follows:
 RW = read/write,
 SC = self clearing,
 WO = write only,
 RO = read only,
 LH = latch high, clear on read of register,
 LL = latch low, clear on read of register,
 NASR = Not Affected by Software Reset
Table 5.33 SMI Register Mapping
REGISTER # DESCRIPTION GROUP
0 Basic Control Register Basic
1 Basic Status Register Basic
2 PHY Identifier 1 Extended
3 PHY Identifier 2 Extended
4 Auto-Negotiation Advertisement Register Extended
5 Auto-Negotiation Link Partner Ability Register Extended
6 Auto-Negotiation Expansion Register Extended
16 Silicon Revision Register Vendor-specific
17 Mode Control/Status Register Vendor-specific
18 Special Modes Vendor-specific
20 TSTCNTL – Testability/Configuration Control Vendor-specific
21 TSTREAD1 – Testability data Read for LSB Vendor-specific
22 TSTREAD2 – Testability data Read for MSB Vendor-specific
23 TSTWRITE – Testability/Configuration data Write Vendor-specific
27 Control / Status Indication Register Vendor-specific
28 Special internal testability controls Vendor-specific
29 Interrupt Source Register Vendor-specific
30 Interrupt Mask Register Vendor-specific
31 PHY Special Control/Status Register Vendor-specific