Datasheet

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Revision 0.8 (06-12-08) 32 SMSC LAN83C185
DATASHEET
Table 5.28 Special Control/Status Indications Register 27: Vendor-Specific
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved SWRST_FAST SQEOFF VCOOFF_LP Reserved Reserved Reserved Reserved Reserved XPOL AUTONEGS
Table 5.29 Special Internal Testability Control Register 28: Vendor-Specific
1514131211109876543210
Reserved
Table 5.30 Interrupt Source Flags Register 29: Vendor-Specific
151413121110987654321 0
Reserved INT7 INT6 INT5 INT4 INT3 INT2 INT1 Reserved
Table 5.31 Interrupt Mask Register 30: Vendor-Specific
1514131211109876543210
Reserved Mask Bits
Table 5.32 PHY Special Control/Status Register 31: Vendor-Specific
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Reserved Special Autodone Reserved GPO2 GPO1 GPO0 Enable
4B5B
Reserved Speed Indication Reserved Scramble
Disable