Datasheet

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Revision 0.8 (06-12-08) 27 SMSC LAN83C185
DATASHEET
Chapter 5 Registers
Table 5.1 Control Register: Register 0 (Basic)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset Loopback Speed Select A/N Enable Power Down Isolate Restart A/N Duplex Mode Collision Test Reserved
Table 5.2 Status Register: Register 1 (Basic)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
100Base-
T4
100Base-
TX
Full Duplex
100Base-
TX
Half
Duplex
10Base-T
Full
Duplex
10Base-T
Half
Duplex
Reserved A/N
Complete
Remote
Fault
A/N
Ability
Link
Status
Jabber
Detect
Extended
Capability
Table 5.3 PHY ID 1 Register: Register 2 (Extended)
1514131211109876543210
PHY ID Number (Bits 3-18 of the Organizationally Unique Identifier - OUI)
Table 5.4 PHY ID 2 Register: Register 3 (Extended)
1514131211109876543210
PHY ID Number (Bits 19-24 of the Organizationally Unique
Identifier - OUI)
Manufacturer Model Number Manufacturer Revision Number
Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Reserved Remote
Fault
Reserved Symmetric
Pause
Operation
Asymmetric
Pause
Operation
100Base-T4 100Base-TX
Full Duplex
100Base-
TX
10Base-T
Full
Duplex
10Base-T IEEE 802.3 Selector Field