Datasheet

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)

Datasheet

Revision 0.8 (06-12-08) 26 SMSC LAN83C185

DATASHEET

The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400

ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a

microcontroller.

The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing

of the data is shown in Figure 4.4 and Figure 4.5.

The timing relationships of the MDIO signals are further described in Section 6.1, "Serial

Management Interface (SMI) Timing," on page 50.

Figure 4.4 MDIO Timing and Frame Structure - READ Cycle

Figure 4.5 MDIO Timing and Frame Structure - WRITE Cycle

DI0

Read Cycle

...

32 1's 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0

...

D15 D14 D0

Preamble

Start of

Frame

Code

PHY Address Register Address

Turn

Around

Data

Data From Phy

Data To Phy

DIO

...

32 1's 0 1 10 A4A3A2A1A0R4R3R2R1R0

Write Cycle

D15 D14 D1 D0

...