Datasheet

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185 17 Revision 0.8 (06-12-08)
DATASHEET
The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is
bypassed the 5
th
transmit data bit is equivalent to TX_ER.
Note that encoding can be bypassed only when the MAC interface is configured to operate in MII
mode.
Table 4.1 4B/5B Code Table
CODE
GROUP SYM
RECEIVER
INTERPRETATION
TRANSMITTER
INTERPRETATION
11110 0 0 0000 DATA 0 0000 DATA
01001 1 1 0001 1 0001
10100 2 2 0010 2 0010
10101 3 3 0011 3 0011
01010 4 4 0100 4 0100
01011 5 5 0101 5 0101
01110 6 6 0110 6 0110
01111 7 7 0111 7 0111
10010 8 8 1000 8 1000
10011 9 9 1001 9 1001
10110 A A 1010 A 1010
10111 B B 1011 B 1011
11010 C C 1100 C 1100
11011 D D 1101 D 1101
11100 E E 1110 E 1110
11101 F F 1111 F 1111
11111 I IDLE Sent after /T/R until TX_EN
11000 J First nibble of SSD, translated to “0101”
following IDLE, else RX_ER
Sent for rising TX_EN
10001 K Second nibble of SSD, translated to
“0101” following J, else RX_ER
Sent for rising TX_EN
01101 T First nibble of ESD, causes de-assertion
of CRS if followed by /R/, else assertion
of RX_ER
Sent for falling TX_EN
00111 R Second nibble of ESD, causes
deassertion of CRS if following /T/, else
assertion of RX_ER
Sent for falling TX_EN
00100 H Transmit Error Symbol Sent for rising TX_ER
00110 V INVALID, RX_ER if during RX_DV INVALID
11001 V INVALID, RX_ER if during RX_DV INVALID
00000 V INVALID, RX_ER if during RX_DV INVALID
00001 V INVALID, RX_ER if during RX_DV INVALID