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SMSC LAN83C185 DATASHEET Revision 0.8 (06-12-08)

Datasheet

PRODUCT FEATURES

LAN83C185

High Performance Single

Chip Low Power 10/100

Ethernet Physical Layer

Transceiver (PHY)

 Single Chip Ethernet Phy

 Fully compliant with IEEE 802.3/802.3u standards

 10BASE-T and 100BASE-TX support

 Supports Auto-negotiation and Parallel Detection

 Automatic Polarity Correction

 Integrated DSP with Adaptive Equalizer

 Baseline Wander (BLW) Correction

 Media Independent Interface (MII)

 802.3u compliant register functions

 Vendor Specific register functions

 Comprehensive power management features

 General power-down mode

 Energy Detect power-down mode

 Low profile 64-pin TQFP package; lead-free RoHS

compliant package also available

 Single +3.3V supply with 5V tolerant I/O

 0.18 micron technology

 Low power consumption

 Operating Temperature 0° C to 70° C

 Internal +1.8V Regulator

Applications

LAN on Motherboard

10/100 PCMCIA/CardBus Applications

Embedded Telecom Applications

Video Record/Playback Systems

Cable Modems And Set-Top Boxes

Digital Televisions

Wireless Access Points

ORDER NUMBERS:

LAN83C185-JD FOR 64-PIN TQFP PACKAGE

LAN83C185-JT FOR 64-PIN TQFP LEAD-FREE ROHS COMPLIANT PACKAGE

Summary of content (60 pages)

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LAN83C185 High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) PRODUCT FEATURES Datasheet Single Chip Ethernet Phy Fully compliant with IEEE 802.3/802.3u standards 10BASE-T and 100BASE-TX support Supports Auto-negotiation and Parallel Detection Automatic Polarity Correction Integrated DSP with Adaptive Equalizer Baseline Wander (BLW) Correction Media Independent Interface (MII) 802.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.5 5.6 5.4.1 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet List of Figures Figure 1.1 Figure 2.1 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 5.1 Figure 7.1 LAN83C185 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 100Base-TX Data Path . . . . . . .
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet List of Tables Table 2.1 LAN83C185 64-PIN TQFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.1 MII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 LED Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.42 Register 17 - Mode Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.43 Register 18 - Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.44 Register 20 - TSTCNTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 1 General Description The SMSC LAN83C185 is a low-power, highly integrated analog interface IC for high-performance embedded Ethernet applications. The LAN83C185 requires only a single +3.3V supply.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet NC1 AVDD4 AVSS5 AVDD3 AVSS4 EXRES1 AVSS3 AVDD2 NC2 RXP RXN AVDD1 AVSS2 TXP TXN AVSS1 Chapter 2 Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GPO0/MII 1 48 CRS GPO1/PHYAD4 2 47 COL GPO2 3 46 nINT MODE0 4 45 TXD3 MODE1 5 44 TXD2 MODE2 6 43 VDD3 VSS1 7 42 TXD1 VDD1 8 41 TXD0 TEST0 9 40 VSS7 TEST1 10 39 TX_EN CLK_FREQ 11
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 2.1 LAN83C185 64-PIN TQFP Pinout PIN NO. PIN NAME PIN NO.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 3 Pin Description This chapter describes in detail the functionality of each of the five main architectural blocks. The term “block” defines a stand-alone entity on the floor plan of the chip. 3.1 I/O Signals I – Input. Digital TTL levels. O – Output. Digital TTL levels. AI – Input. Analog levels. AO – Output. Analog levels. AI/O – Input or Output. Analog levels.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 3.1 MII Signals (continued) PIN NO. 37 SIGNAL NAME TX_ER (TXD4) TYPE I I DESCRIPTION MII Transmit Error: When driven high, the 4B/5B encode process substitutes the Transmit Error code-group (/H/) for the encoded data word. This input is ignored in 10BaseT operation. In Symbol Interface (5B Decoding) mode, this signal becomes the MII Transmit Data 4: the MSB of the 5-bit symbol code-group.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 3.4 Configuration Inputs PIN NO. SIGNAL NAME TYPE DESCRIPTION 2 PHYAD4 I PHY Address Bit 4: set the default address of the PHY. 20 PHYAD3 I PHY Address Bit 3: set the default address of the PHY. 19 PHYAD2 I PHY Address Bit 2: set the default address of the PHY. 17 PHYAD1 I PHY Address Bit 1: set the default address of the PHY.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 3.5 General Signals (continued) PIN NO. 1 SIGNAL NAME GPO0 TYPE O DESCRIPTION General Purpose Output 0 – General Purpose Output signal. Driven by bits in registers 27 and 31. (Muxed with MII Select) This pin should be pulled-down or left floating – Do Not Pull Up. Table 3.6 10/100 Line Interface PIN NO.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 3.9 Power Signals (continued) PIN NO. SIGNAL NAME TYPE DESCRIPTION 60 AVSS4 Power Analog Ground 62 AVSS5 Power Analog Ground 13 VREG Power +3.3V Internal Regulator Input Voltage 14 VDD_CORE Power +1.8V Ring (Core voltage) - required for capacitance connection. 8 VDD1 Power +3.3V Digital Power 18 VDD2 Power +3.3V Digital Power 43 VDD3 Power +3.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 4 Architecture Details 4.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is bypassed the 5th transmit data bit is equivalent to TX_ER. Note that encoding can be bypassed only when the MAC interface is configured to operate in MII mode. Table 4.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 4.1 4B/5B Code Table (continued) CODE GROUP SYM 00010 V INVALID, RX_ER if during RX_DV INVALID 00011 V INVALID, RX_ER if during RX_DV INVALID 00101 V INVALID, RX_ER if during RX_DV INVALID 01000 V INVALID, RX_ER if during RX_DV INVALID 01100 V INVALID, RX_ER if during RX_DV INVALID 10000 V INVALID, RX_ER if during RX_DV INVALID 4.2.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 100M PLL RX_CLK MAC MII 25MHz by 4 bits 25MHz by 4 bits MII 4B/5B Decoder 25MHz by 5 bits Descrambler and SIPO 125 Mbps Serial NRZI Converter A/D Converter NRZI MLT-3 MLT-3 Converter DSP: Timing recovery, Equalizer and BLW Correction MLT-3 Magnetics RJ45 MLT-3 MLT-3 CAT-5 6 bit Data Figure 4.2 Receive Data Path 4.3 100Base-TX Receive The receive data path is shown in Figure 4.2.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 4.3.8 Receiver Errors During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RX_ER signal is asserted and arbitrary data is driven onto the RXD[3:0] lines.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 4.5 10Base-T Receive The 10Base-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics. It recovers the receive clock from the signal and uses this clock to recover the NRZI data stream. This 10M serial data is converted to 4-bit data nibbles which are passed to the controller across the MII at a rate of 2.5MHz. This 10M receiver uses the following blocks: 4.5.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 4.6.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Power-down reset Link status down Setting register 0, bit 9 high (auto-negotiation restart) On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast Link Pulses (FLP). These are bursts of link pulses from the 10M transmitter. They are shaped as Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 4.7.2 Re-starting Auto-negotiation Auto-negotiation can be re-started at any time by setting register 0, bit 9. Auto-negotiation will also restart if the link is broken at any time. A broken link is caused by signal loss. This may occur because of a cable break, or because of an interruption in the signal transmitted by the Link Partner.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by the I/O port of a microcontroller. The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing of the data is shown in Figure 4.4 and Figure 4.5.
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Table 5.1 Control Register: Register 0 (Basic) 15 14 13 12 11 10 9 8 7 6 Reset Loopback Speed Select A/N Enable Power Down Isolate Restart A/N Duplex Mode Collision Test 5 4 3 2 1 0 Reserved Table 5.
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15 14 13 Next Page Acknowledge Remote Fault 12 11 Reserved 10 9 8 7 6 5 4 Pause 100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T 3 2 1 0 IEEE 802.3 Selector Field Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended) 15 14 13 12 11 10 9 8 7 6 5 Reserved 4 3 2 1 0 Parallel Detect Fault Link Partner Next Page Able Next Page Able Page Received Link Partner A/N Able 28 DATASHEET Table 5.
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14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 IEEE Reserved Table 5.12 Register 11 (Extended) 15 14 13 12 11 10 9 8 7 6 IEEE Reserved Table 5.13 Register 12 (Extended) 15 14 13 12 11 10 9 8 7 6 IEEE Reserved 29 DATASHEET Table 5.14 Register 13 (Extended) 15 14 13 12 11 10 9 8 7 6 IEEE Reserved Table 5.
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15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 Silicon Revision 2 1 0 Reserved Table 5.18 Mode Control/ Status Register 17: Vendor-Specific 15 14 13 12 11 10 9 8 7 Reserved FASTRIP EDPWRDOWN Reserved LOWSQEN MDPREBP FARLOOPBACK FASTEST 6 5 Reserved 4 3 2 1 0 REFCLKEN PHYADBP Force Good Link Status ENERGYON Reserved Table 5.
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14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 READ_DATA Table 5.23 TSTREAD1 Register 22: Vendor-Specific 15 14 13 12 11 10 9 8 7 6 5 READ_DATA Table 5.24 TSTWRITE Register 23: Vendor-Specific 15 14 13 12 11 10 9 8 7 6 WRITE_DATA 31 DATASHEET Table 5.25 Register 24: Vendor-Specific 15 14 13 12 11 10 9 8 7 6 Reserved Table 5.
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14 13 Reserved 12 11 10 9 8 7 6 5 4 3 SWRST_FAST SQEOFF VCOOFF_LP Reserved Reserved Reserved Reserved Reserved XPOL 2 1 0 AUTONEGS Table 5.29 Special Internal Testability Control Register 28: Vendor-Specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Table 5.30 Interrupt Source Flags Register 29: Vendor-Specific 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 Reserved 32 DATASHEET Table 5.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.1 SMI Register Mapping The following registers are supported (register numbers are in decimal): Table 5.33 SMI Register Mapping REGISTER # 5.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.34 Register 0 - Basic Control ADDRESS NAME DESCRIPTION MODE DEFAULT 0.15 Reset 1 = software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits in this register. RW/ SC 0 0.14 Loopback 1 = loopback mode, 0 = normal operation RW 0 0.13 Speed Select 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is enabled (0.12 = 1).
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.35 Register 1 - Basic Status (continued) ADDRESS NAME DESCRIPTION MODE DEFAULT 1.3 Auto-Negotiate Ability 1 = able to perform auto-negotiation function 0 = unable to perform auto-negotiation function RO 1 1.2 Link Status 1 = link is up, 0 = link is down RO/ LL 0 1.1 Jabber Detect 1 = jabber condition detected 0 = no jabber condition detected RO/ LH 0 1.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.38 Register 4 - Auto Negotiation Advertisement (continued) ADDRESS NAME DESCRIPTION MODE DEFAULT 4.8 100Base-TX Full Duplex 1 = TX with full duplex, 0 = no TX full duplex ability RW Set by MODE[2:0] bus 4.7 100Base-TX 1 = TX able, 0 = no TX ability RW 1 4.6 10Base-T Full Duplex 1 = 10Mbps with full duplex 0 = no 10Mbps with full duplex ability RW Set by MODE[2:0] bus 4.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.40 Register 6 - Auto Negotiation Expansion ADDRESS NAME DESCRIPTION MODE DEFAULT RO 0 6.15:5 Reserved 6.4 Parallel Detection Fault 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic RO/ LH 0 6.3 Link Partner Next Page Able 1 = link partner has next page ability 0 = link partner does not have next page ability RO 0 6.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.42 Register 17 - Mode Control/Status (continued) ADDRESS NAME DESCRIPTION MODE DEFAULT RW 0 17.8 FASTEST Auto-Negotiation Test Mode 0 = normal operation 1 = activates test mode 17.7:5 Reserved Write as 0, ignore on read. 17.4 Reserved Reserved Must be left at 0 RW 0 17.3 PHYADBP 1 = PHY disregards PHY address in SMI access write. RW 0 17.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.43 Register 18 - Special Modes (continued) ADDRESS 18.4:0 NAME PHYAD DESCRIPTION MODE DEFAULT PHY Address. The PHY Address is used for the SMI address and for the initialization of the Cipher (Scrambler) key. Refer to Section 5.4.9.1, "Physical Address Bus PHYAD[4:0]," on page 45 for more details. RW, NASR PHYAD MODE DEFAULT Table 5.44 Register 20 - TSTCNTL ADDRESS NAME DESCRIPTION 20.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.47 Register 23 - TSTWRITE ADDRESS 23.15:0 NAME WRITE_DATA DESCRIPTION This field contains the data that will be written to a specific register on the “Programming” transaction. MODE DEFAULT RW 0 MODE DEFAULT RW 0 Table 5.48 Register 27 - Special Control/Status Indications ADDRESS NAME DESCRIPTION 27.15:13 Reserved 27.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.50 Register 29 - Interrupt Source Flags (continued) ADDRESS NAME DESCRIPTION MODE DEFAULT 29.6 INT6 1 = Auto-Negotiation complete 0 = not source of interrupt RO/ LH 0 29.5 INT5 1 = Remote Fault Detected 0 = not source of interrupt RO/ LH 0 29.4 INT4 1 = Link Down (link status negated) 0 = not source of interrupt RO/ LH 0 29.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.52 Register 31 - PHY Special Control/Status (continued) ADDRESS NAME DESCRIPTION MODE DEFAULT 31.4:2 Speed Indication HCDSPEED value: [001]=10Mbps Half-duplex [101]=10Mbps Full-duplex [010]=100Base-TX Half-duplex [110]=100Base-TX Full-duplex RO 000 31.1 Reserved Write as 0; ignore on Read RW 0 31.0 Scramble Disable 0 = enable data scrambling 1 = disable data scrambling, RW 0 5.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.4.2 Collision Detect A collision is the occurrence of simultaneous transmit and receive operations. The COL output is asserted to indicate that a collision has been detected. COL remains active for the duration of the collision. COL is changed asynchronously to both RX_CLK and TX_CLK. The COL output becomes inactive during full duplex mode. COL may be tested by setting register 0, bit 7 high.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts the nINT interrupt if the ENERGYON interrupt is enabled. The first and possibly the second packet to activate ENERGYON may be lost. When 17.13 is low, energy detect power-down is disabled. 5.4.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Phy Address = 0 LED output = active high Phy Address = 1 LED output = active low VDD LED1-LED4 ~10K ohms ~270 ohms ~270 ohms LED1-LED4 Figure 5.1 PHY Address Strapping on LEDS The ACTIVITY LED output is driven active when CRS is active (high). When CRS becomes inactive, the Activity LED output is extended by 128ms. The LINKON LED output is driven active whenever the PHY detects a valid link.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.4.9.2 Mode Bus – MODE[2:0] The MODE[2:0] bus controls the configuration of the 10/100 digital block. Table 5.53 MODE[2:0] Bus DEFAULT REGISTER BIT VALUES MODE[2:0] MODE DEFINITIONS REGISTER 0 REGISTER 4 [13,12,10,8] [8,7,6,5] 000 10Base-T Half Duplex. Auto-negotiation disabled. 0000 N/A 001 10Base-T Full Duplex. Auto-negotiation disabled. 0001 N/A 010 100Base-TX Half Duplex.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.5.1.2 General Characteristics ITEM SPEC UNITS Full Scale Input voltage 3.0 Differential (peak-to-peak) V Input Common Mode 1.6-2.0 V 5.5.2 REMARK Gain dependent. 100M PLL Three main functions are included in the 100M PLL: a clock multiplier to generate a 125MHz clock, a phase interpolator to synchronize the receive clock to the receive data, and a transmit wave-shaping delay reference. 5.5.2.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.5.6.1 Functional Description The Data recovery PLL has two modes of operation: Frequency Mode and Data Mode. In frequency mode, the VCO locks to the external reference clock. In Data mode, the VCO locks to the incoming data. When the PLL switches to Data mode, the VCO is held. It is released on an incoming data edge.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.6 5.6.1 DSP Block General Description The “DSP Block” includes the following modules: DSP Core (Equalizer, Timing and BLW correction), Testability / Configuration module (Testability / Configuration control), Testability / Configuration Registers (not including any SMI registers) and the Multiplexers (for the testability / configuration signals).
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 6 Electrical Characteristics The timing diagrams and limits in this section define the requirements placed on the external signals of the Phy. 6.1 Serial Management Interface (SMI) Timing MDC MDIO (Write) T1.1 T1.2 Valid Data MDIO (Read) T1.3 T1.4 Valid Data PARAMETER DESCRIPTION MIN TYP MAX UNITS T1.1 MDC frequency T1.2 MDC to MDIO (Write) delay 0 T1.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 6.2 6.2.1 100Base-TX Timings 100M MII Receive Timing RX_CLK RXD[3:0] RX_DV RX_ER Valid Data T2.1 PARAMETER DESCRIPTION MIN T2.2 TYP MAX UNITS T2.1 Receive signals setup to RX_CLK rising 10 ns T2.2 Receive signals hold from RX_CLK rising 10 ns 6.2.2 RX_CLK frequency 25 MHz RX_CLK Duty-Cycle 40 % NOTES 100M MII Transmit Timing TX_CLK TXD[3:0] TX_EN TX_ER Valid Data T3.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 6.3 6.3.1 10Base-T Timings 10M MII Receive Timing RX_CLK RXD[3:0] RX_DV RX_ER Valid Data T4.1 PARAMETER DESCRIPTION T4.2 MIN TYP MAX UNITS T4.1 Receive signals setup to RX_CLK rising 10 ns T4.2 Receive signals hold from RX_CLK rising 10 ns RX_CLK frequency 25 MHz RX_CLK Duty-Cycle 40 % Receive signals setup to RX_CLK rising 6.3.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 6.4 Reset Timing T6.1 nRST T6.2 T6.3 Configuration signals T6.4 Output drive PARAMETER DESCRIPTION MIN TYP MAX UNITS T6.1 Reset Pulse Width 100 us T6.2 Configuration input setup to nRST rising 200 ns T6.3 Configuration input hold after nRST rising 400 ns T6.4 Output Drive after nRST rising 20 SMSC LAN83C185 53 DATASHEET 800 ns NOTES 20 clock cycles for 25 MHz clock Revision 0.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 6.5 DC Characteristics 6.5.1 Operating Conditions Supply Voltage +3.3V +/- 10% Operating Temperature 0°C to 70°C 6.5.2 Power Consumption 6.5.2.1 Power Consumption Device Only Power measurements taken under the following conditions: Temperature: +25° C Device VDD: +3.30 V Table 6.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 6.5.2.2 Power Consumption Device and System Components Power measurements taken under the following conditions: Temperature: +25° C Device VDD: +3.30 V Table 6.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 6.5.3 DC Characteristics - Input and Output Buffers Table 6.3 MII Bus Interface Signals PIN NO. NAME VIH VIL 41 TXD0 +2.0 V +0.8 V 42 TXD1 +2.0 V +0.8 V 44 TXD2 +2.0 V +0.8 V 45 TXD3 +2.0 V +0.8 V 37 TX_ER/TXD4 +2.0 V +0.8 V 39 TX_EN +2.0 V +0.8 V 38 IOH IOL VOL VOH TX_CLK -8 mA +8 mA +0.4 V VDD – +0.4 V 32 RXD0 -8 mA +8 mA +0.4 V VDD – +0.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 6.4 LAN Interface Signals PIN NO. NAME 51 TXP 50 TXN 55 RXP 54 RXN VIH VIL IOH IOL VOL VOH See Table 6.10, “100Base-TX Transceiver Characteristics,” on page 59 and Table 6.11, “10BASE-T Transceiver Characteristics,” on page 59. Table 6.5 LED Signals PIN NO. NAME VIH VIL IOH IOL VOL VOH 16 SPEED100 +2.0 V +0.8 V -12 mA +24 mA +0.4 V VDD – +0.4 V 17 LINKON +2.0 V +0.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 6.6 Configuration Inputs (continued) PIN NO. NAME VIH 12 REG_EN 1 MII VIL IOH IOL VOL VOH -4 mA +8 mA +0.4 V VDD – +0.4 V IOH IOL VOL VOH Table 6.7 General Signals PIN NO. NAME VIH VIL 1 GPO0 -4 mA +8 mA +0.4 V VDD – +0.4 V 2 GPO1 -4 mA +8 mA +0.4 V VDD – +0.4 V 3 GPO2 -4 mA +8 mA +0.4 V VDD – +0.4 V 46 nINT -4 mA +8 mA +0.4 V VDD – +0.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 6.9 Internal Pull-Up / Pull-/Down Configurations (continued) PIN NO. NAME PULL-UP OR PULL-DOWN TYPE 16 SPEED100 Pull-up 30 uA 17 LINKON Pull-up 30 uA 19 ACTIVITY Pull-up 30 uA 20 FDUPLEX Pull-up 30 uA 46 nINT Pull-up 30 uA Table 6.
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 7 Package Outline Figure 7.1 64 Pin TQFP Package Outline, 10X10X1.4 Body, 2 MM Footprint Table 7.1 64 Pin TQFP Package Parameters MIN NOMINAL MAX REMARKS A A1 A2 D D1 E E1 H L L1 e ~ 0.05 1.35 11.80 9.80 11.80 9.80 0.09 0.45 ~ 1.60 0.15 1.45 12.20 10.20 12.20 10.20 0.20 0.75 ~ θ 0o ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.