Datasheet

Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
SMSC LAN7500/LAN7500i 17 Revision 1.0 (11-01-10)
DATASHEET
2.1 Pin Assignments
1
Ethernet
+1.2V Bias
Power Supply
Input
VDD12BIAS P Refer to Chapter 6, "Application Diagrams," on
page 36 and the LAN7500/LAN7500i reference
schematics for additional connection information.
1
Ethernet PLL
+1.2V Power
Supply Input
VDD12PLL P Refer toChapter 6, "Application Diagrams," on
page 36 and the LAN7500/LAN7500i reference
schematics for additional connection information.
Exposed
pad on
package
bottom
(Figure 2.1)
Ground VSS P Common Ground
Table 2.8 56-QFN Package Pin Assignments
PIN
NUM PIN NAME
PIN
NUM PIN NAME
PIN
NUM PIN NAME
PIN
NUM PIN NAME
1 TDI 15 VDD33A 29 EECS 43 TR0N
2 TCK 16 USBRBIAS 30 VDD12CORE 44 TR0P
3 TMS 17 VDD12USBPLL 31 GPIO0/LED0 45 VDD12A
4 TDO 18 GPIO8 32 GPIO1/LED1 46 TR1N
5 XI 19 VDDVARIO 33 GPIO2/LED2 47 TR1P
6 XO 20 VDD12CORE 34 GPIO3/LED3 48 VDD12A
7 VDDVARIO 21 GPIO9 35 GPIO4/LED4 49 VDD12BIAS
8 VDD12CORE 22 GPIO10 36 VDD12CORE 50 VDD12PLL
9 SW_MODE 23 VDD12CORE 37 VDDVARIO 51 TR2N
10 GPIO7 24 VDDVARIO 38 GPIO5/PME 52 TR2P
11 VDD12CORE 25 GPIO11 39 TEST 53 VDD12A
12 USBDM 26 EECLK 40 GPIO6/
PME_MODE_SEL
54 TR3N
13 USBDP 27 EEDI 41 ETHRBIAS 55 TR3P
14 VBUS_DET 28 EEDO 42 nRESET/
PME_CLEAR
56 VDD12A
EXPOSED PAD
MUST BE CONNECTED TO VSS
Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad (continued)
NUM PINS NAME SYMBOL
BUFFER
TYPE DESCRIPTION