Datasheet

Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
SMSC LAN7500/LAN7500i 15 Revision 1.0 (11-01-10)
DATASHEET
Table 2.5 Ethernet PHY Pins
NUM PINS NAME SYMBOL
BUFFER
TYPE DESCRIPTION
1
Crystal Input XI ICLK External 25 MHz crystal input.
Note: This pin can also be driven by a single-
ended clock oscillator. When this
method is used, XO should be left
unconnected
1
Crystal
Output
XO OCLK External 25 MHz crystal output.
1
Ethernet
TX/RX
Positive
Channel 0
TR0P AIO Transmit/Receive Positive Channel 0.
1
Ethernet
TX/RX
Negative
Channel 0
TR0N AIO Transmit/Receive Negative Channel 0.
1
Ethernet
TX/RX
Positive
Channel 1
TR1P AIO Transmit/Receive Positive Channel 1.
1
Ethernet
TX/RX
Negative
Channel 1
TR1N AIO Transmit/Receive Negative Channel 1.
1
Ethernet
TX/RX
Positive
Channel 2
TR2P AIO Transmit/Receive Positive Channel 2.
1
Ethernet
TX/RX
Negative
Channel 2
TR2N AIO Transmit/Receive Negative Channel 2.
1
Ethernet
TX/RX
Positive
Channel 3
TR3P AIO Transmit/Receive Positive Channel 3.
1
Ethernet
TX/RX
Negative
Channel 3
TR3N AIO Transmit/Receive Negative Channel 3.
1
External PHY
Bias Resistor
ETHRBIAS AI Used for the internal bias circuits. Connect to an
external 8.06K 1.0% resistor to ground.