Datasheet

Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
Revision 1.0 (11-01-10) 14 SMSC LAN7500/LAN7500i
DATASHEET
Table 2.3 JTAG Pins
NUM PINS NAME SYMBOL
BUFFER
TYPE DESCRIPTION
1
JTAG Test
Data Out
TDO VO8 JTAG (IEEE 1149.1) data output.
1
JTAG Test
Data Input
TDI VIS
(PU)
JTAG (IEEE 1149.1) data input.
Note: When not used, tie this pin to
VDDVARIO.
1
JTAG Test
Clock
TCK VIS
(PD)
JTAG (IEEE 1149.1) test clock.
Note: When not used, tie this pin to VSS.
1
JTAG Test
Mode Select
TMS VIS
(PU)
JTAG (IEEE 1149.1) test mode select.
Note: When not used, tie this pin to
VDDVARIO.
Table 2.4 USB Pins
NUM PINS NAME SYMBOL
BUFFER
TYPE DESCRIPTION
1
USB
DMINUS
USBDM AIO Note: The functionality of this pin may be
swapped to USB DPLUS via the Port
Swap bit of Configuration Flags 0.
1
USB
DPLUS
USBDP AIO Note: The functionality of this pin may be
swapped to USB DMINUS via the Port
Swap bit of Configuration Flags 0.
1
External USB
Bias Resistor.
USBRBIAS AI Used for setting HS transmit current level and on-
chip termination impedance. Connect to an
external 12K 1.0% resistor to ground.