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SMSC LAN7500/LAN7500i Revision 1.0 (11-01-10)

DATASHEET

Datasheet

PRODUCT FEATURES

LAN7500/LAN7500i

Hi-Speed USB 2.0 to

10/100/1000 Ethernet Controller

Highlights

 Single Chip Hi-Speed USB 2.0 to 10/100/1000

Ethernet Controller

 10/100/1000 Ethernet MAC with Full-Duplex Support

 10/100/1000 Ethernet PHY with HP Auto-MDIX

 Integrated USB 2.0 Hi-Speed Device Controller

 Integrated USB 2.0 Hi-Speed PHY

 Implements Reduced Power Operating Modes

 Supports EEPROM-less Operation for Reduced BOM

 NetDetach provides automatic USB attach/detach

when Ethernet cable is connected/removed

Target Applications

 Embedded Systems / CE Devices

 Set-Top Boxes / PVR’s

 Networked Printers

 USB Port Replicators

 Standalone USB to Ethernet Dongles

 Test Instrumentation / Industrial

Key Benefits

 USB Device Controller

— Fully compliant with USB Specification Revision 2.0

— Supports HS (480 Mbps) and FS (12 Mbps) modes

— Four endpoints supported

— Supports vendor specific commands

— Integrated USB 2.0 PHY

— Remote wakeup supported

 High-Performance 10/100/1000 Ethernet Controller

— Fully compliant with IEEE802.3/802.3u/802.3ab

— Integrated Ethernet MAC and PHY

— 10BASE-T, 100BASE-TX, and 1000BASE-T support

— Full- and half-duplex capability (only full-duplex

operation at 1000Mbps)

— Full-duplex flow control

— Preamble generation and removal

— Automatic 32-bit CRC generation and checking

— 9 KB jumbo frame support

— Automatic payload padding and pad removal

— Loop-back modes

— Supports checksum offloads

(IPv4, IPv6, TCP, UDP)

— Supports Microsoft NDIS 6.2 large send offload

— Supports IEEE 802.1q VLAN tagging

– Ability to add and strip IEEE 802.1q VLAN tags

– VLAN tag based packet filtering (all 4096 VIDs)

— Flexible address filtering modes

– 33 exact matches (unicast or multicast)

– 512-bit hash filter for multicast frames

– Pass all multicast

– Promiscuous unicast/multicast modes

– Inverse filtering

– Pass all incoming with status report

— Wakeup packet support

– Perfect DA frame, wakeup frame, magic packet,

broadcast frame, IPv6 & IPv4 TCP SYN

– 8 programmable 128-bit wakeup frame filters

— ARP and NS offload

— PME pin support

— Integrated Ethernet PHY

– Auto-negotiation

– Automatic polarity detection and correction

– HP Auto-MDIX support

– Link status change wake-up detection

— Support for 5 status LEDs

— Supports various statistical counters

 Power and I/Os

— Various low power modes

— 12 GPIOs

— Supports bus-powered and self-powered operation

— Variable voltage I/O supply (2.5V/3.3V)

 Miscellaneous Features

— EEPROM Controller

— IEEE 1149.1 (JTAG) Boundary Scan

— Requires single 25 MHz crystal

 Software

— Windows XP/ Vista / Windows 7 Driver

— Linux Driver

— Win CE Driver

—MAC OS Driver

— EEPROM/Manufacturing Utility for Windows/DOS

— PXE Support

— DOS ODI Driver

 Packaging

— 56-pin QFN (8x8 mm) lead-free RoHS compliant

 Environmental

— Commercial Temperature Range (0°C to +70°C)

— Industrial Temperature Range (-40°C to +85°C)

Summary of content (56 pages)

PAGE 1
LAN7500/LAN7500i Hi-Speed USB 2.
PAGE 2
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Order Numbers: LAN7500-ABZJ for 56 pin, QFN lead-free RoHS compliant package (0 to +70°C temp range) LAN7500i-ABZJ for 56 pin, QFN lead-free RoHS compliant package (-40 to +85°C temp range) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.
PAGE 3
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.
PAGE 4
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.4 7.5 7.6 7.3.5.1 VDDVARIO & Magnetics = 2.5V .................................................................................... 43 7.3.5.2 VDDVARIO & Magnetics = 3.3V .................................................................................... 44 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AC Specifications . . . . . . . . . . . .
PAGE 5
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet List of Figures Figure 1.1 Figure 2.1 Figure 4.1 Figure 4.2 Figure 5.1 Figure 5.2 Figure 6.1 Figure 6.2 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Figure 8.1 Figure 8.2 LAN7500/LAN7500i System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LAN7500/LAN7500i 56-QFN Pin Assignments (TOP VIEW). . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Application . . . . . . .
PAGE 6
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet List Of Tables Table 1.1 IEEE 1149.1 Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.1 GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.2 EEPROM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Chapter 1 Introduction 1.1 USB JTAG Block Diagram USB PHY USB 2.0 Device Controller TAP Controller FIFO Controller Receive Filtering Engine 10/100/ 1000 Ethernet MAC Ethernet PHY EEPROM Controller SRAM Ethernet EEPROM LAN7500/LAN7500i Figure 1.1 LAN7500/LAN7500i System Diagram 1.1.1 Overview The LAN7500/LAN7500i is a high performance Hi-Speed USB 2.0 to 10/100/1000 Ethernet controller.
PAGE 8
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 1.1.2 USB The USB portion of the LAN7500/LAN7500i integrates a Hi-Speed USB 2.0 device controller and USB PHY. The USB device controller contains a USB low-level protocol interpreter which implements the USB bus protocol, packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with autonomous error handling. The USB device controller is capable of operating in USB 2.
PAGE 9
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 1.1.6 Host Offloading The LAN7500/LAN7500i supports a variety of TCP/UDP/IP checksum offloads to reduce the burden on the host processor. For Ethernet receive frames, the device can be configured to validate the IP checksum and UDP/TCP checksum. Both IPv4 and IPv6 packets are supported. A raw checksum across the layer 3 packet can also be provided.
PAGE 10
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet The implemented IEEE 1149.1 instructions and their op codes are shown in Table 1.1. Table 1.1 IEEE 1149.1 Op Codes INSTRUCTION OP CODE COMMENT Bypass 111 Mandatory Instruction Sample/Preload 010 Mandatory Instruction EXTEST 000 Mandatory Instruction Clamp 011 Optional Instruction HIGHZ 100 Optional Instruction IDCODE 001 Optional Instruction Note: All digital I/O pins support IEEE 1149.1 operation.
PAGE 11
Hi-Speed USB 2.
PAGE 12
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 2.1 GPIO Pins NUM PINS 1 NAME SYMBOL BUFFER TYPE Indicator LED0 LED0 VOD8 Used in conjunction with LED1. May be programmed to indicate Link and Speed or Link and Speed and Activity. General Purpose I/O 0 GPIO0 VIS/VO8/ VOD8 (PU) This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input.
PAGE 13
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 2.1 GPIO Pins (continued) NUM PINS BUFFER TYPE NAME SYMBOL PME Mode Select PME_MODE_SEL VIS (PU) This pin may serve as the PME_MODE_SEL input when PME mode of operation is in effect. Refer to Chapter 4, "PME Operation," on page 30 for additional information.
PAGE 14
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 2.3 JTAG Pins NUM PINS NAME SYMBOL BUFFER TYPE 1 JTAG Test Data Out TDO VO8 JTAG (IEEE 1149.1) data output. JTAG Test Data Input TDI VIS (PU) JTAG (IEEE 1149.1) data input. 1 1 JTAG Test Clock TCK VIS (PD) JTAG (IEEE 1149.1) test clock. JTAG Test Mode Select TMS VIS (PU) JTAG (IEEE 1149.1) test mode select. 1 DESCRIPTION Note: Note: Note: When not used, tie this pin to VDDVARIO.
PAGE 15
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 2.5 Ethernet PHY Pins NUM PINS NAME SYMBOL BUFFER TYPE Crystal Input XI ICLK DESCRIPTION External 25 MHz crystal input. Note: 1 This pin can also be driven by a singleended clock oscillator. When this method is used, XO should be left unconnected 1 Crystal Output XO OCLK TR0P AIO Transmit/Receive Positive Channel 0. 1 Ethernet TX/RX Positive Channel 0 TR0N AIO Transmit/Receive Negative Channel 0.
PAGE 16
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 2.6 Miscellaneous Pins NUM PINS NAME SYMBOL System Reset nRESET BUFFER TYPE VIS (PU) DESCRIPTION This active-low pin allows external hardware to reset the device. Note: 1 1 PME Clear PME_CLEAR VIS (PU) Detect Upstream VBUS Power VBUS_DET IS_5V (PD) Assertion of nRESET is required following power-on. This pin may serve as the PME_CLEAR input when PME mode of operation is in effect.
PAGE 17
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 2.7 I/O Power Pins, Core Power Pins, and Ground Pad (continued) NUM PINS NAME SYMBOL BUFFER TYPE VDD12BIAS P 1 Ethernet +1.2V Bias Power Supply Input Refer to Chapter 6, "Application Diagrams," on page 36 and the LAN7500/LAN7500i reference schematics for additional connection information. 1 Ethernet PLL +1.
PAGE 18
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 2.2 Buffer Types Table 2.9 Buffer Types BUFFER TYPE VIS IS_5V VO6 VOD6 VO8 VOD8 PU DESCRIPTION Variable voltage Schmitt-triggered Input 5V Tolerant Schmitt-triggered Input Variable voltage output with 6mA sink and 6mA source Variable voltage open-drain output with 6mA sink Variable voltage output with 8mA sink and 8mA source Variable voltage open-drain output with 8mA sink 50uA (typical) internal pull-up.
PAGE 19
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Chapter 3 EEPROM Controller (EPC) LAN7500/LAN7500i may use an external EEPROM to store the default values for the USB descriptors and the MAC address. The EEPROM controller supports most “93C56 or 93C66” type 256/512 byte EEPROMs. A total of nine address bits are used for connection to the device. Note: A 3-wire style 2K/4K EEPROM that is organized for 256/512 x 8-bit operation must be used.
PAGE 20
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.
PAGE 21
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.2 describes the Configuration Flags 0 byte. If a configuration descriptor exists in the EEPROM, it will override the values in Configuration Flags 0. Table 3.2 Configuration Flags 0 BITS 7 DESCRIPTION Port Swap This bit facilitates swapping the mapping of USBDP and USBDM. 0 = USBDP maps to the USB D+ line and USBDM maps to the USB D- line. 1 = USBDP maps to the USB D- line. USBDM maps to the USB D+ line.
PAGE 22
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.2 Configuration Flags 0 (continued) BITS 1 DESCRIPTION Remote Wakeup Support 0 = Device does not support remote wakeup. 1 = Device supports remote wakeup. 0 Power Method 0 = Device is bus powered. 1 = Device is self powered. Table 3.3 describes the Configuration Flags 1. Table 3.3 Configuration Flags 1 BITS 7 DESCRIPTION LED2_FUNCTION This bit specifies the functionality of LED2. 0 = Link and Activity LED. 1 = Activity LED.
PAGE 23
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.4 describes the GPIO PME flags. Table 3.4 GPIO PME Flags BITS DESCRIPTION 7 GPIO PME Enable Setting this bit enables the assertion of the GPIO5 pin, as a result of a Wakeup (GPIO) pin, Magic Packet, or PHY Link Up. The host processor may use the GPIO5 pin to asynchronously wake up, in a manner analogous to a PCI PME pin. 0 = The device does not support GPIO PME signaling. 1 = The device supports GPIO PME signaling.
PAGE 24
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.4 GPIO PME Flags (continued) BITS 1 DESCRIPTION PME Magic Packet Enable When GPIO PME WOL Select indicates WOL is selected, this bit enables/disables Magic Packet detection and wakeup. 0 = Magic Packet event wakeup disabled. 1 = Magic Packet event wakeup enabled. Note: 0 This bit is ignored if GPIO PME WOL Select indicates WOL event wakeup not supported.
PAGE 25
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 3.4 An Example of EEPROM Format Interpretation Table 3.6 and Table 3.7 provide an example of how the contents of a EEPROM are formatted. Table 3.6 is a dump of the EEPROM memory (256-byte EEPROM), while Table 3.7 illustrates, byte by byte, how the EEPROM is formatted. The industrial version of the device is used in the example. Table 3.
PAGE 26
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.
PAGE 27
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.7 EEPROM Example - 256 Byte EEPROM (continued) EEPROM ADDRESS EEPROM CONTENTS (HEX) 1Fh 04 GPIO[11:8] Wake Enables - GPIO10 Used For Wakeup Signaling 20h 8A GPIO PME Flags - PME Signaling Enabled via Low Level, Push-Pull Driver, Magic Packet WOL selected. 21h 7C Configuration Flags 1 - LED2 is Link and Activity LED, GPIO pins 0 to 4 function as LEDs, SW_MODE pin active low in SUSPEND2 state.
PAGE 28
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.
PAGE 29
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 3.
PAGE 30
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Chapter 4 PME Operation LAN7500/LAN7500i provides a mechanism for waking up a host system via PME mode of operation. PME signaling is only available while the device is operating in the self powered mode and a properly configured EEPROM is attached. Figure 4.1 illustrates a typical application. Host Processor Chipset HC DP/DM Enable PME VBUS_DET Embedded Controller (EC) PME_CLEAR LAN7500/ LAN7500i PME_MODE_SEL EEPROM Figure 4.
PAGE 31
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet The Host Processor is connected to a Chipset containing the Host USB Controller (HC). The USB Host Controller interfaces to LAN7500/LAN7500i via the DP/DM USB signals. An Embedded Controller (EC) signals the Chipset and the Host processor to power up via an Enable signal. The EC interfaces to LAN7500/LAN7500i via four signals. The PME signal is an input to the EC from the device that indicates the occurrence of a wakeup event.
PAGE 32
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Figure 4.2 flowcharts PME operation while in Internal PHY mode.
PAGE 33
Hi-Speed USB 2.
PAGE 34
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Chapter 5 NetDetach Operation 5.1 NetDetach NetDetach is a mode of operation where the device detaches from the USB bus after the Ethernet cable is disconnected. This is advantageous for mobile devices, as an attached USB device may prevent the Host CPU from entering the ACPI C3 state. Allowing the CPU to enter the C3 state maximizes battery life, as the C3 state is the lowest of the four APCI power states.
PAGE 35
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Ethernet 1 Insert Ethernet Cable 2 USB Electricals Attach 3 LAN7500/LAN7500i enumerates and the driver is loaded SMSC LAN7500/ LAN7500i Figure 5.2 LAN7500/LAN7500i Attach SMSC LAN7500/LAN7500i 35 DATASHEET Revision 1.
PAGE 36
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Chapter 6 Application Diagrams This section provides typical application diagrams for the following: 6.
PAGE 37
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 6.2 Power Supply & Twisted Pair Interface Diagram LAN7500/LAN7500i VDD12USBPLL CBYPASS VDD12PLL CBYPASS Circuitry within the dotted line is for Channel 0. Duplicate this circuit for Channels 1, 2 and 3. VDD12BIAS (x4) VDD12A CBYPASS CBYPASS Magnetics RJ45 Power Supply 1.2V VDD12CORE (x6) TR0P CBYPASS x6 Power Supply 3.3V 1 2 3 4 5 6 7 8 75 TR0N VDD33A CBYPASS 1000 pF 2 kV 0.022uF Power Supply 2.5V – 3.3V 49.
PAGE 38
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Chapter 7 Operational Characteristics 7.1 Absolute Maximum Ratings* Supply Voltage (VDDVARIO) (Note 7.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V Analog Supply Voltage (VDD12A) (Note 7.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +1.5V Analog USB Supply Voltage (VDD33A) (Note 7.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.
PAGE 39
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.2 Operating Conditions** Supply Voltage (VDDVARIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.25V to +3.6V Supply Voltage (VDD12A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.14V to +1.26V Analog USB Supply Voltage (VDD33A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +3.
PAGE 40
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.3.1.2 VDDVARIO & Magnetics = 3.3V Table 7.2 SUSPEND0 Current & Power (VDDVARIO & Magnetics = 3.3V) PARAMETER MIN TYPICAL MAX UNIT Supply current (VDDVARIO, VDD33A = 3.3V) 3.5 mA Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL, VDD12PLL, VDD12A = 1.2V) 453 mA Power Dissipation (Device Only) 556 mW Power Dissipation (Device and Ethernet components) 1231 mW 7.3.2 SUSPEND1 7.3.2.1 VDDVARIO & Magnetics = 2.5V Table 7.
PAGE 41
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.3.3 SUSPEND2 (Self-Powered) 7.3.3.1 VDDVARIO & Magnetics = 2.5V Table 7.5 SUSPEND2 (Self-Powered) Current & Power (VDDVARIO & Magnetics = 2.5V) PARAMETER MIN TYPICAL MAX UNIT Supply current (VDD33A = 3.3V) 0.5 mA Supply current (VDDVARIO = 2.5V) 0.2 mA Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL, VDD12PLL, VDD12A = 1.2V) 2.0 mA Power Dissipation (Device Only) 4.
PAGE 42
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.3.4 SUSPEND2 (Bus-Powered) 7.3.4.1 VDDVARIO & Magnetics = 2.5V Table 7.7 SUSPEND2 (Bus-Powered) Current & Power (VDDVARIO & Magnetics = 2.5V) PARAMETER MIN TYPICAL MAX UNIT Supply current (VDD33A = 3.3V) 0.5 mA Supply current (VDDVARIO = 2.5V) 0.2 mA Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL, VDD12PLL, VDD12A = 1.2V) 1.0 mA Power Dissipation (Device Only) 3.
PAGE 43
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.3.5 Operational 7.3.5.1 VDDVARIO & Magnetics = 2.5V Table 7.9 Operational Current & Power (VDDVARIO & Magnetics = 2.5V) PARAMETER MIN TYPICAL MAX UNIT 1000BASE-T Full Duplex (USB High-Speed) Supply current (VDD33A = 3.3V) 6.8 mA Supply current (VDDVARIO = 2.5V) 3.1 mA Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL, VDD12PLL, VDD12A = 1.
PAGE 44
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.3.5.2 VDDVARIO & Magnetics = 3.3V Table 7.10 Operational Current & Power (VDDVARIO & Magnetics = 3.3V) PARAMETER MIN TYPICAL MAX UNIT 1000BASE-T Full Duplex (USB High-Speed) Supply current (VDDVARIO, VDD33A = 3.3V) 9.8 mA Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL, VDD12PLL, VDD12A = 1.
PAGE 45
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.4 DC Specifications Table 7.11 I/O Buffer Characteristics PARAMETER 2.5V TYP SYMBOL MIN Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 0.64 1.15 Positive-Going Threshold VIHT 0.81 SchmittTrigger Hysteresis (VIHT - VILT) VHYS 102 Input Leakage (VIN = VSS or VDDVARIO) IIH -10 Input Capacitance CIN 3.3V TYP MAX UNITS NOTES VIS Type Input Buffer V 3.6 V 1.41 1.
PAGE 46
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Note 7.5 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add +/- 50uA per-pin (typical). Note 7.6 This is the total 5.5V input leakage for the entire device. Note 7.7 XI can optionally be driven from a 25MHz single-ended clock oscillator. Table 7.
PAGE 47
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Table 7.14 10BASE-T Transceiver Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V Note 7.14 Receiver Differential Squelch Threshold VDS 300 420 585 mV Note 7.14 Min/max voltages guaranteed as measured with 100Ω resistive load. 7.5 AC Specifications This section details the various AC timing specifications of the device.
PAGE 48
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.5.2 Power Sequence Timing Power supplies must adhere to the following rules:  All power supplies of the same voltage must be powered up/down together.  There is no power-up sequencing requirement, however all power supplies must reach operational levels within the time periods specified in Table 7.15.
PAGE 49
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.5.3 Power-On Reset Timing Figure 7.3 illustrates the nRESET timing requirements in relation to power-on. A hardware reset (nRESET assertion) is required following power-on. For proper operation, nRESET must be asserted for no less than trstia. The nRESET pin can be asserted at any time, but must not be deasserted before tpurstd after all external power supplies have reached operational levels.
PAGE 50
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.5.4 Reset Timing Figure 7.3 illustrates the nRESET pin timing requirements. When used, nRESET must be asserted for no less than trstia. Note: A hardware reset (nRESET assertion) is required following power-on. Refer to Section 7.5.3, "Power-On Reset Timing," on page 49 for additional information. trstia nRESET Figure 7.4 nRESET Timing Table 7.17 nRESET Timing Values SYMBOL trstia DESCRIPTION MIN nRESET input assertion time Revision 1.
PAGE 51
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.5.5 EEPROM Timing The following specifies the EEPROM timing requirements for the device: tcsl EECS tcshckh tckcyc tckh tckl tcklcs l EECLK tckldis tdvckh tckhinvld EEDO tdsckh tdhckh EEDI tdhcsl tcshdv EEDI (VERIFY) Figure 7.5 EEPROM Timing Table 7.
PAGE 52
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.5.6 JTAG Timing This section specifies the JTAG timing of the device. Please refer to Section 1.1.10, "TAP Controller," on page 9 for additional details. ttckp ttckhl ttckhl TCK (Input) tsu th TDI, TMS (Inputs) tdov tdoinvld TDO (Output) Figure 7.6 JTAG Timing Table 7.19 JTAG Timing Values SYMBOL DESCRIPTION ttckp TCK clock period ttckhl TCK clock high/low time MIN MAX 66.67 ttckp*0.4 UNITS ns ttckp*0.
PAGE 53
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet 7.6 Clock Circuit The device can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
PAGE 54
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Chapter 8 Package Outline Figure 8.1 LAN7500/LAN7500i 56-QFN Package Table 8.1 LAN7500/LAN7500i 56-QFN Dimensions MIN NOMINAL MAX REMARKS A 0.70 0.85 1.00 Overall Package Height A1 0.00 0.02 0.05 Standoff A2 - - 0.90 Mold Cap Thickness D/E 7.85 8.00 8.15 X/Y Body Size D1/E1 7.55 7.75 7.95 X/Y Mold Cap Size D2/E2 5.80 5.90 6.00 X/Y Exposed Pad Size L 0.30 0.40 0.50 Terminal Length b 0.18 0.25 0.
PAGE 55
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Notes: 1. All dimensions are in millimeters unless otherwise noted. 2. 3. Position tolerance of each terminal and exposed pad is +/- 0.05 mm at maximum material condition. Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip. The pin 1 identifier may vary, but is always located within the zone indicated. Figure 8.
PAGE 56
Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Chapter 9 Revision History Table 9.1 Customer Revision History REVISION LEVEL AND DATE Rev. 1.0 (11-01-10) Revision 1.0 (11-01-10) SECTION/FIGURE/ENTRY All CORRECTION Initial Release.