Datasheet

Micrel, Inc. KS8721BL/SL
June 2009
32
M9999-062509-1.3
VCC
R
10k
C
10µF
D1
KS8721BL/SL
RST
D1: 1N4148
Figure 11. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from
CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than
VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.
Reference Circuit for Strapping Option Configuration
Figure 12 shows the reference circuit for strapping option pins.
KS8721BL/SL
LED pin
3.3V
Reference circuits for unmanaged programming through LED ports.
KS8721BL/SL
LED pin
3.3V
Pull-Up
Pull-down
Figure 12. Reference Circuit, Strapping Option Pins